Difference between revisions of "Unaxis VLR Etch - Process Control Data"

Revision as of 11:34, 20 April 2022

Work In Progress

This article is still under construction. It may contain factual errors. Content is subject to change.

InP Ridge Etch: TO BE ADDED 90s Etch Sample Size: EXAMPLE: 1x1cm, ~30-40% SiO₂ masking (NingC's pattern). Silicon carrier, no adhesive.
Date	Sample#	Etch Rate (nm/min)	Etch Selectivity (InP/SiO2)	Comments	SEM Images
3/30/22	NP_Unaxis_02	1413	14.6		[1] [2]
3/9/22	NP_Unaxis_01	1297	15.3	~30-40% SiO₂ masking (NingC's pattern)	[1] [2]

@@ Line 4: / Line 4: @@
 [[PECVD1-(PlasmaTherm 790)|PECVD SiO2]] hardmask, patterned on [[Stepper 1 (GCA 6300)|Stepper #2 (AutoStep 200)]] & [[ICP Etch 1 (Panasonic E626I)|Panasonic ICP #1]]
 {| class="wikitable"
-| colspan="6" |'''InP Ridge Etch''':  TO BE ADDED
+| colspan="6" |'''InP Ridge Etch''':  TO BE ADDED 90s Etch
 Sample Size: EXAMPLE: 1x1cm, ~30-40% SiO<sub>2</sub> masking (NingC's pattern). Silicon carrier, no adhesive.
 |-
@@ Line 14: / Line 14: @@
 |SEM Images
 |-
-|1/26/22
+|3/30/22
+|NP_Unaxis_02
-|<small>EXAMPLE ONLY</small>
+|1413
-|~400nm
+|14.6
-|240 nm left
-|~30-40% SiO<sub>2</sub> masking (NingC's pattern)
 |
+|[https://wiki.nanotech.ucsb.edu/w/images/8/84/Unaxis_02_45D_002.jpg <nowiki>[1]</nowiki>] [https://wiki.nanotech.ucsb.edu/w/images/6/60/Unaxis_02_CS_002.jpg <nowiki>[2]</nowiki>]
+|-
+|3/9/22
+|NP_Unaxis_01
+|1297
+|15.3
+|~30-40% SiO<sub>2</sub> masking (NingC's pattern)
+|[https://wiki.nanotech.ucsb.edu/w/images/3/3e/Unaxis_01_45D_002.jpg <nowiki>[1]</nowiki>] [https://wiki.nanotech.ucsb.edu/w/images/7/71/Unaxis_01_CS_001.jpg <nowiki>[2]</nowiki>]
 |}