Difference between revisions of "Oxford ICP Etcher - Process Control Data"
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(updated tables, split into "sample size dpeendence" table) |
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| colspan="6" |'''InP Ridge Etch''': 60°C, 3mT, 800W/65W, Cl2=18, H2=15, CH4=10sccm, time=5min00sec (300sec) |
| colspan="6" |'''InP Ridge Etch''': 60°C, 3mT, 800W/65W, Cl2=18, H2=15, CH4=10sccm, time=5min00sec (300sec) |
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| − | + | Sample Size: 1x1cm, ~30-40% SiO<sub>2</sub> masking (NingC's pattern). Silicon carrier, no adhesive. |
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|Date |
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|1/26/22 |
|1/26/22 |
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| − | |<small> |
+ | |<small>NP_?</small> |
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| − | === |
+ | ===Dependence on Sample Size=== |
We have found that the size of the InP piece loaded (no adhesive, onto Silicon carrier wafer) affects the etch rate, but does not affect the etch profile - ie. etches are still smooth and vertical, but rate varies with sample area. |
We have found that the size of the InP piece loaded (no adhesive, onto Silicon carrier wafer) affects the etch rate, but does not affect the etch profile - ie. etches are still smooth and vertical, but rate varies with sample area. |
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{| class="wikitable" |
{| class="wikitable" |
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| colspan="8" |'''InP Ridge Etch''': 60°C, 3mT, 800W/65W, Cl2=18, H2=15, CH4=10sccm, time=5min05sec (305sec) |
| colspan="8" |'''InP Ridge Etch''': 60°C, 3mT, 800W/65W, Cl2=18, H2=15, CH4=10sccm, time=5min05sec (305sec) |
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| + | Silicon carrier, no adhesive. |
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|Date |
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|0.602 |
|0.602 |
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|64.6nm left |
|64.6nm left |
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| + | |<small>~50% SiO<sub>2</sub> masking (GCA Calibration pattern)</small> |
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|[https://wiki.nanotech.ucsb.edu/w/images/9/90/2022-01-11_Oxford_InP_Ridge_Wiki_Post_-_Cal01.pdf] |
|[https://wiki.nanotech.ucsb.edu/w/images/9/90/2022-01-11_Oxford_InP_Ridge_Wiki_Post_-_Cal01.pdf] |
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|0.563 |
|0.563 |
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|76.4nm left |
|76.4nm left |
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| + | |<small>~50% SiO<sub>2</sub> masking (GCA Calibration pattern)</small> |
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| − | | |
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|[https://wiki.nanotech.ucsb.edu/w/images/d/d1/2022-01-12_Oxford_InP_Ridge_Wiki_Post_-_Cal02.pdf] |
|[https://wiki.nanotech.ucsb.edu/w/images/d/d1/2022-01-12_Oxford_InP_Ridge_Wiki_Post_-_Cal02.pdf] |
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|0.612 |
|0.612 |
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|71nm left |
|71nm left |
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| + | |<small>~50% SiO<sub>2</sub> masking (GCA Calibration pattern)</small> |
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| − | | |
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|[https://wiki.nanotech.ucsb.edu/w/images/f/ff/2022-01-12_Oxford_InP_Ridge_Wiki_Post_-_Cal03.pdf] |
|[https://wiki.nanotech.ucsb.edu/w/images/f/ff/2022-01-12_Oxford_InP_Ridge_Wiki_Post_-_Cal03.pdf] |
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|1/26/22 |
|1/26/22 |
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| − | |<small> |
+ | |<small>NP_?</small> |
|10 x 10 |
|10 x 10 |
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|100 |
|100 |
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| + | |<small>~30-40% SiO<sub>2</sub> masking (NingC's pattern)</small> |
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| − | | |
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|- |
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|1/26/22 |
|1/26/22 |
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| − | |<small> |
+ | |<small>NP_?</small> |
|1/4 of 50mm wafer |
|1/4 of 50mm wafer |
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|490 |
|490 |
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| + | |<small>~30-40% SiO<sub>2</sub> masking (NingC's pattern)</small> |
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| − | | |
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Revision as of 17:09, 28 January 2022
Data - InP Ridge Etch (Oxford ICP Etcher)
PECVD SiO2 hardmask, patterned on Stepper #2 (AutoStep 200) & Panasonic ICP #1
| InP Ridge Etch: 60°C, 3mT, 800W/65W, Cl2=18, H2=15, CH4=10sccm, time=5min00sec (300sec)
Sample Size: 1x1cm, ~30-40% SiO2 masking (NingC's pattern). Silicon carrier, no adhesive. | |||||
| Date | Sample# | Etch Rate (nm/min) | Etch Selectivity (InP/SiO2) | Comments | SEM Images |
| 1/26/22 | NP_? | ||||
Dependence on Sample Size
We have found that the size of the InP piece loaded (no adhesive, onto Silicon carrier wafer) affects the etch rate, but does not affect the etch profile - ie. etches are still smooth and vertical, but rate varies with sample area.
| InP Ridge Etch: 60°C, 3mT, 800W/65W, Cl2=18, H2=15, CH4=10sccm, time=5min05sec (305sec)
Silicon carrier, no adhesive. | |||||||
| Date | Sample# | Sample Size (dimensions, mm) | Sample Size (area, mm2) | Etch Rate (nm/min) | Etch Selectivity (InP/SiO2) | Comments | SEM Images |
| 1/11/22 | DJ_InPRidge | 4.5 x 2.5 | 11.25 | 0.602 | 64.6nm left | ~50% SiO2 masking (GCA Calibration pattern) | [1] |
| 1/12/22 | DJ_InPRidge | 4.5 x 3 | 13.5 | 0.563 | 76.4nm left | ~50% SiO2 masking (GCA Calibration pattern) | [2] |
| 1/12/22 | DJ_InP#3 | 4.5 x 3 | 13.5 | 0.612 | 71nm left | ~50% SiO2 masking (GCA Calibration pattern) | [3] |
| 1/26/22 | NP_? | 10 x 10 | 100 | ~30-40% SiO2 masking (NingC's pattern) | |||
| 1/26/22 | NP_? | 1/4 of 50mm wafer | 490 | ~30-40% SiO2 masking (NingC's pattern) | |||