ICP Etching Recipes

Back to Dry Etching Recipes.

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

Process Control Data (DSEIII)

• To Be Added

Edge-Bead Removal

Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

• Edge Bead Removal via Photolithography: use a custom metal mask to pattern the photoresist with a flood exposure.
  • If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can mount to a carrier wafer using wax.

High Rate Bosch Etch (DSEIII)

• Bosch Process Recipe and Characterization - Standard recipe on the tool.
  • Recipe Name: "Plasma-Therm Standard DSE" (Production - copy to your Personal category)
  • Standard Bosch Process for high aspect-ratio, high-selectivity Silicon etching.
  • Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
    • To reduce roughening/grassing (black silicon), reduce Dep step time by ~20%.
  • Patterns with different etched areas will have different "optimal" parameters.
  • Approx Selectivity to Photoresist: 60-80 or better. Larger open area, lower selectivity and lower etch rate.

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

• Single Step Silicon Etch Recipe and Characterization
  • Recipe Name: "Nano Trench Etch" (Production - copy to your Personal category)
  • Used instead of Bosch Process, to avoid scalloping on the sidewall.
  • Lower selectivity, lower etch rate, smoother sidewalls.

PlasmaTherm/SLR Fluorine Etcher

Process Control Data (Fluorine ICP Etcher)

• SiO₂ Etching with CHF3/CF4 (FL-ICP)

Si Etching (Fluorine ICP Etcher)

• SiVertHF - Si Vertical Etch using C₄F₈/SF₆/CF₄ and resist mask
  • Etch Rates: Si ≈ 300-350 nm/min; SiO₂ ≈ 30-35 nm/min
  • 89-90 degree etch angle, ie, vertical.
  • Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO₂ etch (below) to remove native oxide on Si. This can be performed in situ before the Si etch.

SiO2 Etching (Fluorine ICP Etcher)

• SiO2 Etching using Ruthenium Hardmask - Full Process Traveler
  • Ning Cao & Bill Mitchell, 2019-06
  • High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.
  • Chemistry: CHF3/CF4
  • Variations in SiO₂ etch Bias Power: 50 / 200 / 400W bias.
  • Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
  • 200W Bias:
    • SiO₂ selectivity to Ru: 38
    • SiO₂ etch rate: 471nm/min
  • 50W Bias:
    • Higher selectivity to photoresist: TBD
    • SiO₂ selectivity to Ru: 36
    • SiO₂ etch rate: 263nm/min
  • This etch is detailed in the following article: W.J. Mitchell et al., JVST-A, May 2021

Photoresist & ARC (Fluorine ICP Etcher)

Chain multiple Recipes in a Flow, to allow you to to do in situ BARC etching, and follow up with in situ Photoresist Strip.

PR/BARC Etch (Fluorine ICP Etcher)

• Etching DUV42P-6 Bottom Anti-Reflection Coating
  • ~60nm thick (2500krpm)
  • O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
  • 1min

Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)

• • O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
  • Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

Cleaning Procedures (Fluorine ICP Etcher)

To Be Added

ICP Etch 1 (Panasonic E626I)

Process Control Data (Panasonic 1)

SiO₂ Etch Process Control (Panasonic 1)

• Test Data of etching SiO2 with CHF3/CF4

SiO₂ Etching (Panasonic 1)

Recipes

• SiO₂ Vertical Etch Recipe Parameters - CHF₃ "SiOVert"
  • Etch rate ≈ 2300Å/min (users must calibrate)
  • Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)

Recipe Variations

Use these to determine how each etch parameter affects the process.

• SiO₂ CHF₃ Etch Variations - CHF3 with varying Bias and Pressure, Slanted SiO2 etching

SiN_x Etching (Panasonic 1)

• SiN_x Etch Rates and Variations - CF₄-O₂

Al Etch (Panasonic 1)

• Al Etch Recipes - Cl₂BCl₃
• AlCl₃ Erosion Issue and the Solution

Cr Etch (Panasonic 1)

• Cr Etch Recipes - Cl₂O₂

Ta Etch (Panasonic 1)

• Ta Etch Recipe - Cl2/BCl3

Ti Etch (Panasonic 1)

• Ti Deep Etch Recipes - Cl₂Ar
  • See E. Parker, et. al. Jnl. Electrochem. Soc., 152 (10) C675-C683 2005.

W-TiW Etch (Panasonic 1)

• Ti-TiW Etch Recipes - SF₆Ar

GaAs-AlGaAs Etch (Panasonic 1)

• GaAs-Nanoscale Etch Recipe - PR mask - Cl₂-BCl₃-Ar
• AlGaAs Etch Recipes - Cl₂N₂
• GaAs DRIE via Etch Recipes - Cl₂-BCl₃-Ar PR passivation

GaN Etch (Panasonic 1)

• GaN Etch Recipes Cl₂N₂
• GaN Selective Etch over AlGaN Recipes BCl₃-SF₆

Photoresist and ARC Etching (Panasonic 1)

Please see the recipes for Panasonic ICP#2 - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

SiC Etch (Panasonic 1)

• SiC Etch Recipes Ni Mask - SF₆

Sapphire Etch (Panasonic 1)

• Sapphire Etch Recipes Ni and PR Mask - BCl₃-Cl₂

Old Deleted Recipes

Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the tool's Supervisor and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

ICP Etch 2 (Panasonic E640)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

Process Control Data (Panasonic 2)

SiO₂ Etch Process Control (Panasonic 2)

• Test Data of etching SiO2 with CHF3/CF4

SiO₂ Etching (Panasonic 2)

Recipes

• SiO₂ Vertical Etch Recipe - CHF₃ "SiOVert"
  • Direct copy of "SiOVert" from ICP#1, see parameters there.
• SiO₂ Vertical Etch Recipe#2 - CF₄/CHF₃
• SiO₂ Nanoscale Etch Recipe - CHF₃/O₂

Recipe Variations

Use these to determine how etch parameters affect the process.

• Angled SiO2 sidewall recipes

SiN_x Etching (Panasonic 2)

• SiN_x Nanoscale Etch Recipe - CHF₃/O₂

Al Etch (Panasonic 2)

• Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry (click for plots of etch rate)

Contributed by Brian Markman, 2018

• BCl3 = 30sccm
• Pressure = 0.50 Pa
• ICP Source RF = 500
• Bias RF = 50W or 250W (250W can burn PR)
• Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
• Etch Rate 50W: 0.66nm/sec
• Etch Rate 250W: 1.0 nm/sec

GaAs Etch (Panasonic 2)

• GaAs Etch Recipes - Panasonic 2 - Cl₂N₂

Photoresist and ARC etching (Panasonic 2)

Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

ARC Etching: DUV-42P or AR6

• O2 = 40 sccm // 0.5 Pa
• ICP = 75W // RF = 75W
• 45 sec for full etching of DUV-42P (same as for AR6; 2018-2019, Demis/BrianT)

UV6-0.8 Etching

Works very well for photoresist stripping

• O2 = 40 sccm // 1.0 Pa
• ICP = 350W // RF = 100W
• Etch Rate = 518.5nm / 1min (2019, Demis)
• 2m30sec to fully remove with ~200% overetch

Ru (Ruthenium) Etch (Panasonic 2)

• Ru Etch - Bill Mitchell 2019-09-19
  • This etch is used in the following publication: W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)

ICP-Etch (Unaxis VLR)

Process Control Data (Unaxis VLR)

• InP Etch Process Control Data

GaAs-AlGaAs Etch (Unaxis VLR)

• GaAs Etch Recipe (Cl₂N₂ 30C)
• AlGaAs Etch Recipe (Cl₂N₂ 30C)

InP-InGaAs-InAlAs Etch (Unaxis VLR)

• InP-based Material Etch Profile (Cl₂N₂Ar200C)
• InP-InGaAs Etch Profile (Cl₂H₂Ar 200C)
• Recipe of Etching SiO₂ Mask for Cl₂ Etch (ICP#2)
• InP Etch Historical Data (Cl₂H₂Ar 200C)
• InP Etch Test
• Lower etch-rate InP Etch (Cl₂N₂ 200C)

GaN Etch (Unaxis VLR)

• GaN Etch Recipe (Cl₂BCl₃N₂Ar 85C)

Oxford ICP Etcher (PlasmaPro 100 Cobra)

Process Control Data (Oxford ICP Etcher)

Process Control Data for "Std InP Ridge Etch" - Calibration / Process testing data taken using the "InP Ridge Etch" process (Cl2/CH4/H2 @ 60°C, SiO₂ Hardmask)

InP Ridge Etch (Oxford ICP Etcher)

InP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).

Low-Temp (60°C) Process

• Low-Temp InP Ridge Etch Characterization - Ning Cao, 2021-09-08
  • Bulk InP etches, no mounting adhesive, pieces on blank Silicon carrier
  • NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
• InP Ridge Process - Basic Traveler

InP Grating Etch (Oxford ICP Etcher)

InP/InGaAsP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).

• InP/InGaAsP Grating Etch Characterization - Ning Cao, 2021-08-26
  • NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
• InP//InGaAsP Grating - Basic Traveler

GaAs Etch (Oxford ICP Etcher)

This recipe also provides a starting point for GaSb-based etches.

• GaAs-based materials - etch recipe - provided by Oxford, not yet qualified internally
• GaAs-based Materials - Basic Traveler

GaN Etch (Oxford ICP Etcher)

• GaN-based materials - etch recipe - provided by Oxford, not yet qualified internally
• GaN-based Materials - Basic Traveler

GaN Atomic Layer Etching (Oxford ICP Etcher)

GaN-ALE Recipe written but still undergoing testing - contact supervisor for use.

Si Deep RIE (PlasmaTherm/Bosch Etch)

This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!
The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
For Deep Silicon Etching, the Plasma-Therm DSE-iii is often used.  Some single-step Silicon etching is still performed on the SLR Fluorine ICP, due to the slower etch rate.

Bosch and Release Etch (Si Deep RIE)

• Bosch and Release Processes
  • Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
  • Etch rate depends on area of exposed silicon being etched.
  • Al₂O₃ mask (ALD or Sputter) has >9000:1 selectivity
  • SiO₂ (PECVD) mask has ~100:1 selectivity
  • Thermal SiO₂ has ~300:1 selectivity.

Single-step Si Etching (not Bosch Process!) (Si Deep RIE)

• Single-step Si Vertical Etch Recipe - SF₆-C₄F₈-Ar