Difference between revisions of "ICP Etching Recipes"

From UCSB Nanofab Wiki
Jump to navigation Jump to search
(→‎ICP Etch 2 (Panasonic E640): unfinished Al2O3 etching on ICP2)
Line 3: Line 3:
 
=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=
  
=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=
 
==High Rate Bosch Etch (DSEIII)==
  
==High Rate Bosch Etch (DSEIII)==
−
*[[media:10-Si_Etch_Bosch_DSEIII.pdf|Bosch Process]]
 +
*[[media:10-Si Etch Bosch DSEIII.pdf|Bosch Process]]
 
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==
  
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==
−
*[[media:10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf|Single Step Process]]
 +
*[[media:10-Si Etch Single Step Smooth Sidewall DSEIII.pdf|Single Step Process]]
   
 
=[[Si Deep RIE (PlasmaTherm/Bosch Etch)]]=
  
=[[Si Deep RIE (PlasmaTherm/Bosch Etch)]]=
 
==Bosch and Release Etch (Si Deep RIE)==
  
==Bosch and Release Etch (Si Deep RIE)==
−
*[[media:10-Si_Etch_Bosch_Release_DRIE.pdf|Bosch and Release Processes]]
 +
*[[media:10-Si Etch Bosch Release DRIE.pdf|Bosch and Release Processes]]
 
**Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
  
**Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
 
**Etch rate depends on area of exposed silicon being etched.
 
**Etch rate depends on area of exposed silicon being etched.
Line 31: Line 31:
 
==Al Etch (Panasonic 1)==
  
==Al Etch (Panasonic 1)==
 
*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - Cl<sub>2</sub>BCl<sub>3</sub>]]
  
*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - Cl<sub>2</sub>BCl<sub>3</sub>]]
−
*[[media:32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf|AlCl<sub>3</sub> Erosion Issue and the Solution]]
 +
*[[media:32-Reducing AlCl3 Corrosion with CHF3 plasma.pdf|AlCl<sub>3</sub> Erosion Issue and the Solution]]
   
 
==Cr Etch (Panasonic 1)==
  
==Cr Etch (Panasonic 1)==
Line 44: Line 44:
 
==GaAs-AlGaAs Etch (Panasonic 1)==
  
==GaAs-AlGaAs Etch (Panasonic 1)==
 
*[[media:Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf|GaAs-Nanoscale Etch Recipe - PR mask - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar]]
  
*[[media:Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf|GaAs-Nanoscale Etch Recipe - PR mask - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar]]
−
*[[media:12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf|AlGaAs Etch Recipes - Cl<sub>2</sub>N<sub>2</sub>]]
 +
*[[media:12-Plasma Etching of AlGaAs-Panasonic ICP-1-Etcher.pdf|AlGaAs Etch Recipes - Cl<sub>2</sub>N<sub>2</sub>]]
 
*[[media:Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf|GaAs DRIE via Etch Recipes - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar PR passivation]]
  
*[[media:Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf|GaAs DRIE via Etch Recipes - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar PR passivation]]
   
 
==GaN Etch (Panasonic 1)==
  
==GaN Etch (Panasonic 1)==
−
*[[media:07-GaN_Etch-Panasonic-ICP-1.pdf|GaN Etch Recipes Cl<sub>2</sub>N<sub>2</sub>]]
 +
*[[media:07-GaN Etch-Panasonic-ICP-1.pdf|GaN Etch Recipes Cl<sub>2</sub>N<sub>2</sub>]]
 
*[[media:Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf|GaN Selective Etch over AlGaN Recipes BCl<sub>3</sub>-SF<sub>6</sub>]]
  
*[[media:Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf|GaN Selective Etch over AlGaN Recipes BCl<sub>3</sub>-SF<sub>6</sub>]]
   
Line 63: Line 63:
 
*[[media:Panasonic2-SiOx-Recipe.pdf|SiO<sub>2</sub> Vertical Etch Recipe - CHF<sub>3</sub> "SiOVert"]]
  
*[[media:Panasonic2-SiOx-Recipe.pdf|SiO<sub>2</sub> Vertical Etch Recipe - CHF<sub>3</sub> "SiOVert"]]
 
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
  
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
−
*[[media:33-Etching_SiO2_with_Vertical_Side-wall.pdf|SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]]
 +
*[[media:33-Etching SiO2 with Vertical Side-wall.pdf|SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]]
 
*[[media:Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf|SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]]
  
*[[media:Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf|SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]]
   
Line 71: Line 71:
 
==Al Etch (Panasonic 2)==
  
==Al Etch (Panasonic 2)==
 
*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]]
  
*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]]
  +
  +
== Al2O3 Etching (Panasonic 2) ==
  +
ALD Al2O3 Etch Rates in BCl3 Chemistry
   
 
==GaAs Etch (Panasonic 2)==
  
==GaAs Etch (Panasonic 2)==
−
*[[media:16-GaAs_etch-ICP-2.pdf|GaAs Etch Recipes - Panasonic 2 - Cl<sub>2</sub>N<sub>2</sub>]]
 +
*[[media:16-GaAs etch-ICP-2.pdf|GaAs Etch Recipes - Panasonic 2 - Cl<sub>2</sub>N<sub>2</sub>]]
   
 
=[[ICP-Etch (Unaxis VLR)]]=
  
=[[ICP-Etch (Unaxis VLR)]]=
 
==GaAs-AlGaAs Etch (Unaxis VLR) ==
  
==GaAs-AlGaAs Etch (Unaxis VLR) ==
−
*[[media:15-GaAs_etch-Unaxis_ICP_etcher.pdf|GaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]]
 +
*[[media:15-GaAs etch-Unaxis ICP etcher.pdf|GaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]]
−
*[[media:14-AlAs-GR-cal_etch-Unaxis_ICP_etcher.pdf|AlGaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]]
 +
*[[media:14-AlAs-GR-cal etch-Unaxis ICP etcher.pdf|AlGaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]]
   
 
==InP-InGaAs-InAlAs Etch (Unaxis VLR)==
  
==InP-InGaAs-InAlAs Etch (Unaxis VLR)==
 
*[[media:UNAXIS-VLR-InP-Etch-200C-Recipe.pdf|InP Etch Recipe (Cl<sub>2</sub>N<sub>2</sub>Ar 200C)]]
  
*[[media:UNAXIS-VLR-InP-Etch-200C-Recipe.pdf|InP Etch Recipe (Cl<sub>2</sub>N<sub>2</sub>Ar 200C)]]
−
*[[media:18-InP-based_etching-Cl2N2Ar.pdf|InP-based Material Etch Profile (Cl<sub>2</sub>N<sub>2</sub>Ar200C)]]
 +
*[[media:18-InP-based etching-Cl2N2Ar.pdf|InP-based Material Etch Profile (Cl<sub>2</sub>N<sub>2</sub>Ar200C)]]
 
*[[media:UNAXIS-VLR-InP-Etch-Ar-200C-Recipe.pdf|Unaxis InP Etch Recipe (Cl<sub>2</sub>H<sub>2</sub> Ar 200C) Parameters]]
  
*[[media:UNAXIS-VLR-InP-Etch-Ar-200C-Recipe.pdf|Unaxis InP Etch Recipe (Cl<sub>2</sub>H<sub>2</sub> Ar 200C) Parameters]]
−
*[[media:17-InP%26InGaAs_etch-Cl2H2Ar-Unaxis-VLR.pdf|InP-InGaAs Etch Profile (Cl<sub>2</sub>H<sub>2</sub> Ar 200C)]]
 +
*[[media:17-InP&InGaAs etch-Cl2H2Ar-Unaxis-VLR.pdf|InP-InGaAs Etch Profile (Cl<sub>2</sub>H<sub>2</sub> Ar 200C)]]
−
*[[media:43-Issue_with_the_etch_of_InP-InGaAs-and-_InAlAs-b.pdf|InGaAs-InAlAs Etch Issure (Cl<sub>2</sub>H<sub>2</sub> Ar 200C)]]
 +
*[[media:43-Issue with the etch of InP-InGaAs-and- InAlAs-b.pdf|InGaAs-InAlAs Etch Issure (Cl<sub>2</sub>H<sub>2</sub> Ar 200C)]]
−
*[[media:50-InP_Etch-2-17-2016.pdf|InP Etch (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)2-17-2016]]
 +
*[[media:50-InP Etch-2-17-2016.pdf|InP Etch (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)2-17-2016]]
−
*[[media:InP_Etch_using_Unaxis_PM1_at_200_C-S6.pdf|InP Etch (Cl<sub>2</sub>H<sub>2</sub>Ar 200C) Start on 6-3-2016]]
 +
*[[media:InP Etch using Unaxis PM1 at 200 C-S6.pdf|InP Etch (Cl<sub>2</sub>H<sub>2</sub>Ar 200C) Start on 6-3-2016]]
−
*[[media:Lower-Etch-Rate_InP_Etch_using_Unaxis_PM1_tool_at_200_C.pdf|Lower etch-rate InP Etch (Cl<sub>2</sub>N<sub>2</sub> 200C)]]
 +
*[[media:Lower-Etch-Rate InP Etch using Unaxis PM1 tool at 200 C.pdf|Lower etch-rate InP Etch (Cl<sub>2</sub>N<sub>2</sub> 200C)]]
   
 
==GaN Etch (Unaxis VLR)==
  
==GaN Etch (Unaxis VLR)==
−
*[[media:09-Plasma_Etching_of_GaN-UnaxisPM1.pdf|GaN Etch Recipe (Cl<sub>2</sub>BCl<sub>3</sub>N<sub>2</sub>Ar 85C)]]
 +
*[[media:09-Plasma Etching of GaN-UnaxisPM1.pdf|GaN Etch Recipe (Cl<sub>2</sub>BCl<sub>3</sub>N<sub>2</sub>Ar 85C)]]
   
 
==GaSb Etch (Unaxis VLR)==
  
==GaSb Etch (Unaxis VLR)==
−
*[[media:InGaAsSb_etch.pdf|GaSb Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 80C)]]
 +
*[[media:InGaAsSb etch.pdf|GaSb Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 80C)]]

Revision as of 18:46, 6 February 2018

Back to Dry Etching Recipes.

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

High Rate Bosch Etch (DSEIII)

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

Si Deep RIE (PlasmaTherm/Bosch Etch)

Bosch and Release Etch (Si Deep RIE)

  • Bosch and Release Processes
    • Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
    • Etch rate depends on area of exposed silicon being etched.
    • Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
    • SiO2 (PECVD) mask has ~100:1 selectivity
    • Thermal SiO2 has ~300:1 selectivity.

Single-step Si Etching (not Bosch Process!) (Si Deep RIE)

ICP Etch 1 (Panasonic E626I)

SiO2 Etching (Panasonic 1)

SiNx Etching (Panasonic 1)

Al Etch (Panasonic 1)

Cr Etch (Panasonic 1)

Ti Etch (Panasonic 1)

W-TiW Etch (Panasonic 1)

GaAs-AlGaAs Etch (Panasonic 1)

GaN Etch (Panasonic 1)

SiC Etch (Panasonic 1)

Sapphire Etch (Panasonic 1)

ICP Etch 2 (Panasonic E640)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

SiO2 Etching (Panasonic 2)

SiNx Etching (Panasonic 2)

Al Etch (Panasonic 2)

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry

GaAs Etch (Panasonic 2)

ICP-Etch (Unaxis VLR)

GaAs-AlGaAs Etch (Unaxis VLR)

InP-InGaAs-InAlAs Etch (Unaxis VLR)

GaN Etch (Unaxis VLR)

GaSb Etch (Unaxis VLR)

Retrieved from "https://wiki.nanofab.ucsb.edu/w/index.php?title=ICP_Etching_Recipes&oldid=154757"