Difference between revisions of "ICP Etching Recipes"

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(→‎ICP Etch 2 (Panasonic E640): added placeholder for Ru etch)
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=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=
 
=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=
 
==High Rate Bosch Etch (DSEIII)==
 
==High Rate Bosch Etch (DSEIII)==
*[[media:10-Si Etch Bosch DSEIII.pdf|Bosch Process]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process]
 +
 
 
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==
 
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==
*[[media:10-Si Etch Single Step Smooth Sidewall DSEIII.pdf|Single Step Process]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Process]
  
 
=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=
 
=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=
==Si Etching ==
+
==Si Etching==
*[[media:SLR - SiVertHF.pdf|SiVertHF]] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
+
 
** Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
+
*[//www.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
** 89-90 degree etch angle, ie, vertical.
+
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
 +
**89-90 degree etch angle, ie, vertical.
 +
 
 
==SiO2 Etching==
 
==SiO2 Etching==
* Recipes available, to be characterized/added.
+
 
 +
*Recipes available, to be characterized/added.
  
 
=[[ICP Etch 1 (Panasonic E626I)]]=
 
=[[ICP Etch 1 (Panasonic E626I)]]=
 
==SiO<sub>2</sub> Etching (Panasonic 1)==
 
==SiO<sub>2</sub> Etching (Panasonic 1)==
*[[media:Panasonic1-SiO-Etch.pdf|SiO<sub>2</sub> Vertical Etch Recipe Parameters - CHF<sub>3</sub> "SiOVert"]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO<sub>2</sub> Vertical Etch Recipe Parameters - CHF<sub>3</sub> "SiOVert"]
 
**Etch rate ≈ 2300Å/min (users must calibrate)
 
**Etch rate ≈ 2300Å/min (users must calibrate)
 
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)
 
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)
*[[media:Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf|SiO<sub>2</sub> CHF<sub>3</sub> Etch Variations]]
+
*[//www.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO<sub>2</sub> CHF<sub>3</sub> Etch Variations]
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Florine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Florine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
 
*[[Test Data of etching SiO2 with CHF3/CF4-ICP1|Test Data of etching SiO2 with CHF3/CF4]]
 
*[[Test Data of etching SiO2 with CHF3/CF4-ICP1|Test Data of etching SiO2 with CHF3/CF4]]
  
 
==SiN<sub>x</sub> Etching (Panasonic 1)==
 
==SiN<sub>x</sub> Etching (Panasonic 1)==
*[[media:Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf|SiN<sub>x</sub> Etch Rates and Variations - CF<sub>4</sub>-O<sub>2</sub>]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiN<sub>x</sub> Etch Rates and Variations - CF<sub>4</sub>-O<sub>2</sub>]
  
 
==Al Etch (Panasonic 1)==
 
==Al Etch (Panasonic 1)==
*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - Cl<sub>2</sub>BCl<sub>3</sub>]]
+
 
*[[media:32-Reducing AlCl3 Corrosion with CHF3 plasma.pdf|AlCl<sub>3</sub> Erosion Issue and the Solution]]
+
*[//www.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl<sub>2</sub>BCl<sub>3</sub>]
 +
*[//www.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl<sub>3</sub> Erosion Issue and the Solution]
  
 
==Cr Etch (Panasonic 1)==
 
==Cr Etch (Panasonic 1)==
*[[media:Panasonic-1-Cr-Etch-revA.pdf|Cr Etch Recipes - Cl<sub>2</sub>O<sub>2</sub>]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl<sub>2</sub>O<sub>2</sub>]
  
 
==Ta Etch (Panasonic 1)==
 
==Ta Etch (Panasonic 1)==
*[[media:104 Ta Etch.pdf|Ta Etch Recipe]] - Cl2/BCl3
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3
  
 
==Ti Etch (Panasonic 1)==
 
==Ti Etch (Panasonic 1)==
*[[media:Panasonic-1-Ti-Etch-Deep-RevA.pdf|Ti Deep Etch Recipes - Cl<sub>2</sub>Ar]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl<sub>2</sub>Ar]
 
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].
 
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].
  
 
==W-TiW Etch (Panasonic 1)==
 
==W-TiW Etch (Panasonic 1)==
*[[media:Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf|Ti-TiW Etch Recipes - SF<sub>6</sub>Ar]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF<sub>6</sub>Ar]
  
 
==GaAs-AlGaAs Etch (Panasonic 1)==
 
==GaAs-AlGaAs Etch (Panasonic 1)==
*[[media:Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf|GaAs-Nanoscale Etch Recipe - PR mask - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar]]
+
 
*[[media:12-Plasma Etching of AlGaAs-Panasonic ICP-1-Etcher.pdf|AlGaAs Etch Recipes - Cl<sub>2</sub>N<sub>2</sub>]]
+
*[//www.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar]
*[[media:Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf|GaAs DRIE via Etch Recipes - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar PR passivation]]
+
*[//www.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl<sub>2</sub>N<sub>2</sub>]
 +
*[//www.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar PR passivation]
  
 
==GaN Etch (Panasonic 1)==
 
==GaN Etch (Panasonic 1)==
*[[media:07-GaN Etch-Panasonic-ICP-1.pdf|GaN Etch Recipes Cl<sub>2</sub>N<sub>2</sub>]]
 
*[[media:Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf|GaN Selective Etch over AlGaN Recipes BCl<sub>3</sub>-SF<sub>6</sub>]]
 
  
== Photoresist and ARC Etching ==
+
*[//www.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl<sub>2</sub>N<sub>2</sub>]
 +
*[//www.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl<sub>3</sub>-SF<sub>6</sub>]
 +
 
 +
==Photoresist and ARC Etching==
 
[https://www.nanotech.ucsb.edu/wiki/index.php/ICP_Etching_Recipes#Photoresist_and_ARC_etching_2 Please see the recipes for Panasonic ICP#2] - the same recipes apply.  
 
[https://www.nanotech.ucsb.edu/wiki/index.php/ICP_Etching_Recipes#Photoresist_and_ARC_etching_2 Please see the recipes for Panasonic ICP#2] - the same recipes apply.  
  
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==SiC Etch (Panasonic 1)==
 
==SiC Etch (Panasonic 1)==
*[[media:Panasonic 1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf|SiC Etch Recipes Ni Mask - SF<sub>6</sub>]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF<sub>6</sub>]
  
 
==Sapphire Etch (Panasonic 1)==
 
==Sapphire Etch (Panasonic 1)==
*[[media:Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf|Sapphire Etch Recipes Ni and PR Mask - BCl<sub>3</sub>-Cl<sub>2</sub>]]
 
  
== Old Deleted Recipes ==
+
*[//www.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl<sub>3</sub>-Cl<sub>2</sub>]
 +
 
 +
==Old Deleted Recipes==
 
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.
 
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.
  
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==SiO<sub>2</sub> Etching (Panasonic 2)==
 
==SiO<sub>2</sub> Etching (Panasonic 2)==
*[[media:Panasonic2-SiOx-Recipe.pdf|SiO<sub>2</sub> Vertical Etch Recipe - CHF<sub>3</sub> "SiOVert"]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO<sub>2</sub> Vertical Etch Recipe - CHF<sub>3</sub> "SiOVert"]
 
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
 
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
*[[media:33-Etching SiO2 with Vertical Side-wall.pdf|SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]]
+
*[//www.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]
*[[media:Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf|SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]]
+
*[//www.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Fluorine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Fluorine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
 
*[[Test Data of etching SiO2 with CHF3/CF4]]
 
*[[Test Data of etching SiO2 with CHF3/CF4]]
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==SiN<sub>x</sub> Etching (Panasonic 2)==
 
==SiN<sub>x</sub> Etching (Panasonic 2)==
*[[media:Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf|SiN<sub>x</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiN<sub>x</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]
  
 
==Al Etch (Panasonic 2)==
 
==Al Etch (Panasonic 2)==
*[[media:Panasonic-1-Al-Etch-RevA.pdf|Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]]
 
  
== Al2O3 Etching (Panasonic 2) ==
+
*[//www.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]
[[:Media:Brian Markman - Al2O3 ICP2 Etch Rates 2018.pdf|ALD Al2O3 Etch Rates in BCl3 Chemistry]] (click for plots of etch rate)
+
 
 +
==Al2O3 Etching (Panasonic 2)==
 +
[//www.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)
  
 
''Contributed by Brian Markman, 2018''
 
''Contributed by Brian Markman, 2018''
* BCl3 = 30sccm
+
 
* Pressure = 0.50 Pa
+
*BCl3 = 30sccm
* ICP Source RF = 500
+
*Pressure = 0.50 Pa
* Bias RF = 50W or 250W (250W can burn PR)
+
*ICP Source RF = 500
* Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
+
*Bias RF = 50W or 250W (250W can burn PR)
* Etch Rate 50W: 0.66nm/sec
+
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
* Etch Rate 250W: 1.0 nm/sec
+
*Etch Rate 50W: 0.66nm/sec
 +
*Etch Rate 250W: 1.0 nm/sec
  
 
==GaAs Etch (Panasonic 2)==
 
==GaAs Etch (Panasonic 2)==
*[[media:16-GaAs etch-ICP-2.pdf|GaAs Etch Recipes - Panasonic 2 - Cl<sub>2</sub>N<sub>2</sub>]]
 
  
== Photoresist and ARC etching ==
+
*[//www.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl<sub>2</sub>N<sub>2</sub>]
 +
 
 +
==Photoresist and ARC etching==
 
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:
 
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:
  
=== ARC Etching: DUV-42P or AR6 ===
+
===ARC Etching: DUV-42P or AR6===
* O2 = 40 sccm // 0.5 Pa
+
 
* ICP = 75W // RF = 75W
+
*O2 = 40 sccm // 0.5 Pa
* 45 sec for full etching of DUV-42P (same for AR6)
+
*ICP = 75W // RF = 75W
 +
*45 sec for full etching of DUV-42P (same for AR6)
  
=== UV6-0.8 Etching ===
+
===UV6-0.8 Etching===
 
Works very well for photoresist stripping
 
Works very well for photoresist stripping
* O2 = 40 sccm // 1.0 Pa
 
* ICP = 350W // RF = 100W
 
* Etch Rate = 518.5nm / 1min
 
* 2m30sec to fully remove with ~200% overetch
 
  
== Ru (Ruthenium) Etch (Panasonic 2) ==
+
*O2 = 40 sccm // 1.0 Pa
* [[ICP2 Ru Etch|Ru Etch]] - ''Data to Come''
+
*ICP = 350W // RF = 100W
 +
*Etch Rate = 518.5nm / 1min
 +
*2m30sec to fully remove with ~200% overetch
 +
 
 +
==Ru (Ruthenium) Etch (Panasonic 2)==
 +
TALK TO BILL BEFORE PUBLISHING WORK USING THIS ETCH.  We are currently writing a paper on this etch.
 +
 
 +
*[https://www.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
 +
**''BillM is currently writing a publication on this etch - please discuss with [[Bill Mitchell|Bill]] before submitting any publications using this etch.''
  
 
=[[ICP-Etch (Unaxis VLR)]]=
 
=[[ICP-Etch (Unaxis VLR)]]=
==GaAs-AlGaAs Etch (Unaxis VLR) ==
+
==GaAs-AlGaAs Etch (Unaxis VLR)==
*[[media:15-GaAs etch-Unaxis ICP etcher.pdf|GaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]]
+
 
*[[media:14-AlAs-GR-cal etch-Unaxis ICP etcher.pdf|AlGaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]]
+
*[//www.nanotech.ucsb.edu/wiki/images/4/4e/15-GaAs_etch-Unaxis_ICP_etcher.pdf GaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]
 +
*[//www.nanotech.ucsb.edu/wiki/images/1/1f/14-AlAs-GR-cal_etch-Unaxis_ICP_etcher.pdf AlGaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]
  
 
==InP-InGaAs-InAlAs Etch (Unaxis VLR)==
 
==InP-InGaAs-InAlAs Etch (Unaxis VLR)==
*[[media:18-InP-based etching-Cl2N2Ar.pdf|InP-based Material Etch Profile (Cl<sub>2</sub>N<sub>2</sub>Ar200C)]]
+
 
*[[media:17-InP&InGaAs etch-Cl2H2Ar-Unaxis-VLR.pdf|InP-InGaAs Etch Profile (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)]]
+
*[//www.nanotech.ucsb.edu/wiki/images/9/90/18-InP-based_etching-Cl2N2Ar.pdf InP-based Material Etch Profile (Cl<sub>2</sub>N<sub>2</sub>Ar200C)]
*[[media:SiO2-Mask Etch Recipe for Unaxis Cl2 Etch.pdf|Recipe of Etching SiO<sub>2</sub> Mask for Cl<sub>2</sub> Etch (ICP#2)]]
+
*[//www.nanotech.ucsb.edu/wiki/images/a/ad/17-InP%26InGaAs_etch-Cl2H2Ar-Unaxis-VLR.pdf InP-InGaAs Etch Profile (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)]
*[[InP Etch Test Result in Details|InP Etch Historical Data (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)]]  
+
*[//www.nanotech.ucsb.edu/wiki/images/6/6e/SiO2-Mask_Etch_Recipe_for_Unaxis_Cl2_Etch.pdf Recipe of Etching SiO<sub>2</sub> Mask for Cl<sub>2</sub> Etch (ICP#2)]
 +
*[[InP Etch Test Result in Details|InP Etch Historical Data (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)]]
 
*[[InP Etch Rate and Selectivity (InP/SiO2)|InP Etch Test]]
 
*[[InP Etch Rate and Selectivity (InP/SiO2)|InP Etch Test]]
*[[media:Lower-Etch-Rate InP Etch using Unaxis PM1 tool at 200 C.pdf|Lower etch-rate InP Etch (Cl<sub>2</sub>N<sub>2</sub> 200C)]]
+
*[//www.nanotech.ucsb.edu/wiki/images/a/ac/Lower-Etch-Rate_InP_Etch_using_Unaxis_PM1_tool_at_200_C.pdf Lower etch-rate InP Etch (Cl<sub>2</sub>N<sub>2</sub> 200C)]
  
 
==GaN Etch (Unaxis VLR)==
 
==GaN Etch (Unaxis VLR)==
*[[media:09-Plasma Etching of GaN-UnaxisPM1.pdf|GaN Etch Recipe (Cl<sub>2</sub>BCl<sub>3</sub>N<sub>2</sub>Ar 85C)]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/d/df/09-Plasma_Etching_of_GaN-UnaxisPM1.pdf GaN Etch Recipe (Cl<sub>2</sub>BCl<sub>3</sub>N<sub>2</sub>Ar 85C)]
  
 
==GaSb Etch (Unaxis VLR)==
 
==GaSb Etch (Unaxis VLR)==
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==Bosch and Release Etch (Si Deep RIE)==
 
==Bosch and Release Etch (Si Deep RIE)==
*[[media:10-Si Etch Bosch Release DRIE.pdf|Bosch and Release Processes]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/0/02/10-Si_Etch_Bosch_Release_DRIE.pdf Bosch and Release Processes]
 
**Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
 
**Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
**Etch rate depends on area of exposed silicon being etched.  
+
**Etch rate depends on area of exposed silicon being etched.
 
**Al<sub>2</sub>O<sub>3</sub> mask (ALD or Sputter) has >9000:1 selectivity
 
**Al<sub>2</sub>O<sub>3</sub> mask (ALD or Sputter) has >9000:1 selectivity
 
**SiO<sub>2</sub> (PECVD) mask has ~100:1 selectivity
 
**SiO<sub>2</sub> (PECVD) mask has ~100:1 selectivity
 
**Thermal SiO<sub>2</sub> has ~300:1 selectivity.
 
**Thermal SiO<sub>2</sub> has ~300:1 selectivity.
 +
 
==Single-step Si Etching (not Bosch Process!) (Si Deep RIE)==
 
==Single-step Si Etching (not Bosch Process!) (Si Deep RIE)==
*[[media:10-Si_Etch_using_DRIE_(single-step).pdf|Single-step Si Vertical Etch Recipe - SF<sub>6</sub>-C<sub>4</sub>F<sub>8</sub>-Ar]]
+
 
 +
*[//www.nanotech.ucsb.edu/wiki/images/d/d2/10-Si_Etch_using_DRIE_%28single-step%29.pdf Single-step Si Vertical Etch Recipe - SF<sub>6</sub>-C<sub>4</sub>F<sub>8</sub>-Ar]

Revision as of 11:23, 4 October 2019

Back to Dry Etching Recipes.

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

High Rate Bosch Etch (DSEIII)

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

PlasmaTherm/SLR Fluorine Etcher

Si Etching

  • SiVertHF - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
    • Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
    • 89-90 degree etch angle, ie, vertical.

SiO2 Etching

  • Recipes available, to be characterized/added.

ICP Etch 1 (Panasonic E626I)

SiO2 Etching (Panasonic 1)

SiNx Etching (Panasonic 1)

Al Etch (Panasonic 1)

Cr Etch (Panasonic 1)

Ta Etch (Panasonic 1)

Ti Etch (Panasonic 1)

W-TiW Etch (Panasonic 1)

GaAs-AlGaAs Etch (Panasonic 1)

GaN Etch (Panasonic 1)

Photoresist and ARC Etching

Please see the recipes for Panasonic ICP#2 - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

SiC Etch (Panasonic 1)

Sapphire Etch (Panasonic 1)

Old Deleted Recipes

Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact Don and he'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

ICP Etch 2 (Panasonic E640)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

SiO2 Etching (Panasonic 2)

SiNx Etching (Panasonic 2)

Al Etch (Panasonic 2)

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry (click for plots of etch rate)

Contributed by Brian Markman, 2018

  • BCl3 = 30sccm
  • Pressure = 0.50 Pa
  • ICP Source RF = 500
  • Bias RF = 50W or 250W (250W can burn PR)
  • Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
  • Etch Rate 50W: 0.66nm/sec
  • Etch Rate 250W: 1.0 nm/sec

GaAs Etch (Panasonic 2)

Photoresist and ARC etching

Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

ARC Etching: DUV-42P or AR6

  • O2 = 40 sccm // 0.5 Pa
  • ICP = 75W // RF = 75W
  • 45 sec for full etching of DUV-42P (same for AR6)

UV6-0.8 Etching

Works very well for photoresist stripping

  • O2 = 40 sccm // 1.0 Pa
  • ICP = 350W // RF = 100W
  • Etch Rate = 518.5nm / 1min
  • 2m30sec to fully remove with ~200% overetch

Ru (Ruthenium) Etch (Panasonic 2)

TALK TO BILL BEFORE PUBLISHING WORK USING THIS ETCH.  We are currently writing a paper on this etch.
  • Ru Etch - Bill Mitchell 2019-09-19
    • BillM is currently writing a publication on this etch - please discuss with Bill before submitting any publications using this etch.

ICP-Etch (Unaxis VLR)

GaAs-AlGaAs Etch (Unaxis VLR)

InP-InGaAs-InAlAs Etch (Unaxis VLR)

GaN Etch (Unaxis VLR)

GaSb Etch (Unaxis VLR)

Si Deep RIE (PlasmaTherm/Bosch Etch)

This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!
The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
For Deep Silicon Etching, the Plasma-Therm DSE-iii is often used.  Some single-step Silicon etching is still performed on the SLR Fluorine ICP, due to the slower etch rate.

Bosch and Release Etch (Si Deep RIE)

  • Bosch and Release Processes
    • Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
    • Etch rate depends on area of exposed silicon being etched.
    • Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
    • SiO2 (PECVD) mask has ~100:1 selectivity
    • Thermal SiO2 has ~300:1 selectivity.

Single-step Si Etching (not Bosch Process!) (Si Deep RIE)