Difference between revisions of "ICP Etching Recipes"

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(→‎Si Etching (Fluorine ICP Etcher): added Al2O3/SiO2 masking procedure)
 
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*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
 
*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
 
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
 
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
 +
*[[Photolithography - Manual Edge-Bead Removal Techniques|Manual PR Edge-Bead Removal]] - using swabs and EBR100.  This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!
  
 
==High Rate Bosch Etch (DSEIII)==
 
==High Rate Bosch Etch (DSEIII)==
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**Patterns with different etched areas will have different "optimal" parameters.
 
**Patterns with different etched areas will have different "optimal" parameters.
 
**Approx Selectivity to Photoresist: 60-80 or better.  Larger open area, lower selectivity and lower etch rate.
 
**Approx Selectivity to Photoresist: 60-80 or better.  Larger open area, lower selectivity and lower etch rate.
 +
 +
===Through Silicon Via etch (DSEiii)===
 +
Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult. 
 +
 +
Instead, we recommend the following process with Al<sub>2</sub>O<sub>3</sub> hardmask:
 +
{| class="wikitable"
 +
|+
 +
! colspan="2" |Process for Through-Wafer Silicon Etching
 +
|-
 +
|Process to etch through ~550µm Silicon
 +
|''<small>[[Demis D. John]], 2022-11-11</small>''
 +
|-
 +
|Deposit 150nm Al<sub>2</sub>O<sub>3</sub> on either:
 +
 +
*[https://wiki.nanotech.ucsb.edu/w/index.php?title=Sputtering_Recipes#Al2O3_deposition_.28IBD.29 Veeco Nexus IBD]
 +
*AJA Sputter [https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_3.29 3]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Al2O3_Deposition_.28Sputter_4.29 4]/[https://wiki.nanotech.ucsb.edu/wiki/Sputtering_Recipes#Materials_Table_.28Sputter_5.29 5] (Check which has Al target installed)
 +
|
 +
|-
 +
|Deposit ~3nm SiO<sub>2</sub>, ''in situ'' (same machine as above)
 +
|This improves adhesion to photoresist.
 +
|-
 +
|Lithography - your preferred method
 +
|
 +
|-
 +
|Etch the [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Al2O3 in Panasonic ICP 1/2]
 +
|Use 50W version.  Overetch by ~20%, will also etch through the thin SiO<sub>2</sub> layer.
 +
|-
 +
|Strip PR - either ''[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_Etch.2FStrip_.28Panasonic_2.29 in situ]'', or via NMP 80°C soak followed by [https://wiki.nanotech.ucsb.edu/wiki/Oxygen_Plasma_System_Recipes#Ashers_.28Technics_PEII.29 PEii Technics ashing].
 +
|''In situ'' PR strip appears to give better + faster results.
 +
|-
 +
|If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:
 +
[https://wiki.nanotech.ucsb.edu/wiki/Logitech_WBS7_-_Procedure_for_Wax_Mounting_with_bulk_Crystalbond_Stick Logitech Wax Mounting Recipe - Bulk Crystal Bond]
 +
 +
 +
If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.
 +
|Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
 +
|-
 +
|Use POLOS spinners with ACE/ISO to clean front and back of wafer.
 +
|This also removes any excess wax if you wax-mounted your wafer.
 +
|-
 +
|DSEiii etch - reduce Dep step to eliminate grassing:
 +
 +
*Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
 +
*Rate ≈ 4.25µm / min
 +
|Can use Lasermonitor and/or Camera to observe when etch is fully through.  Trenches may get black/rough, but then clear up when fully etched.
 +
Record Helium FLOW during recipe run, for next step (if He leaks).
 +
|-
 +
|If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow our of compliance.  This is because the cooling Helium leaks through the wafer when the openings get fully etched through.
 +
Once this happens,
 +
 +
*Leave your wafer in the chamber, then
 +
 +
*Edit recipe to set Helium Cooling (first step only) to "Flow Control Only".  Choose typical flow form normal process from above (Something like ~6sccm?  Not sure.)
 +
|
 +
|-
 +
|Strip Al<sub>2</sub>O<sub>3</sub>/SiO<sub>2</sub> either with HF, or same Pan1/2 dry etch as above.
 +
|
 +
|-
 +
|IF wax-mounted - either
 +
 +
*dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse
 +
 +
OR
 +
 +
*place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
 +
**ACE/ISO clean to remove wax.
 +
|
 +
|}
  
 
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==
 
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==
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**89-90 degree etch angle, ie, vertical.
 
**89-90 degree etch angle, ie, vertical.
 
**Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO<sub>2</sub> etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
 
**Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO<sub>2</sub> etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
 +
**High selectivity to Al2O3 masks. 
 +
***For high aspect ratio Si etching, try [[Atomic Layer Deposition (Oxford FlexAL)|ALD]] [[Atomic Layer Deposition Recipes#Al2O3 deposition .28ALD CHAMBER 3.29|Al<sub>2</sub>O<sub>3</sub>]] (~20-30nm) + [[Atomic Layer Deposition Recipes#SiO2 deposition .28ALD CHAMBER 3.29|SiO<sub>2</sub>]] (2nm, for PR adhesion) hardmasks followed by [https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Al2O3_Etching_.28Panasonic_2.29 Pan2 Al<sub>2</sub>O<sub>3</sub> etch] (will go straight through the thin SiO<sub>2</sub> without additional etch time).  Works well for allowing thin PR's (eg. [[Stepper 3 (ASML)|DUV]] or [[E-Beam Lithography System (JEOL JBX-6300FS)|EBL]] PR's) to enable deep etches.
  
 
==SiO2 Etching (Fluorine ICP Etcher)==
 
==SiO2 Etching (Fluorine ICP Etcher)==
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*Bias RF = 50W or 250W (250W can burn PR)
 
*Bias RF = 50W or 250W (250W can burn PR)
 
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
 
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
*Etch Rate 50W: 0.66nm/sec
+
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
*Etch Rate 250W: 1.0 nm/sec
+
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)
  
 
==GaAs Etch (Panasonic 2)==
 
==GaAs Etch (Panasonic 2)==
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*O2 = 40 sccm // 0.5 Pa
 
*O2 = 40 sccm // 0.5 Pa
 
*ICP = 75W // RF = 75W
 
*ICP = 75W // RF = 75W
*45 sec for full etching of DUV-42P (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])
+
*45 sec for full etching (incl. overetch) of ~60nm [[Stepper Recipes#DUV-42P-6|DUV-42P]] (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])
  
 
===Photoresist Etch/Strip (Panasonic 2)===
 
===Photoresist Etch/Strip (Panasonic 2)===
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*ICP = 350W // RF = 100W
 
*ICP = 350W // RF = 100W
 
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
 
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
*2m30sec to fully remove UV6-0.8 with ~200% overetch
+
*2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, [[Demis D. John|Demis]])
  
 
==Ru (Ruthenium) Etch (Panasonic 2)==
 
==Ru (Ruthenium) Etch (Panasonic 2)==
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==GaSb Etch (Unaxis VLR)==
 
==GaSb Etch (Unaxis VLR)==
 +
''Available - ask staff''
 +
 +
==Cleaning Recipes (Unaxis VLR)==
 +
''To Be Added: Required cleaning time & recipes''
  
 
=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=
 
=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=

Latest revision as of 16:16, 2 December 2022

Back to Dry Etching Recipes.

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

Process Control Data (DSEIII)

Edge-Bead Removal

Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

  • Edge Bead Removal via Photolithography: use a custom metal mask to pattern the photoresist with a flood exposure.
    • If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can mount to a carrier wafer using wax.
  • Manual PR Edge-Bead Removal - using swabs and EBR100. This is prone to error and easy to accidentally leave a blob of PR on the edge - so be extra careful to ensure NO PR is left on the edges!

High Rate Bosch Etch (DSEIII)

  • Bosch Process Recipe and Characterization - Standard recipe on the tool.
    • Recipe Name: "Plasma-Therm Standard DSE" (Production - copy to your Personal category)
    • Standard Bosch Process for high aspect-ratio, high-selectivity Silicon etching.
    • Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
      • To reduce roughening/grassing (black silicon), reduce Dep step time by ~20%.
    • Patterns with different etched areas will have different "optimal" parameters.
    • Approx Selectivity to Photoresist: 60-80 or better. Larger open area, lower selectivity and lower etch rate.

Through Silicon Via etch (DSEiii)

Since the topside clamp requires the removal of photoresist on the outermost ~5-7mm of the wafer, this makes PR incompatible with through-silicon etching (as the outer edges would be etched-through, dropping the inner portion into the chamber). In addition, in practice we have found that thick PR often roughens and burns during long ~30-60min etches, making removal very difficult.

Instead, we recommend the following process with Al2O3 hardmask:

Process for Through-Wafer Silicon Etching
Process to etch through ~550µm Silicon Demis D. John, 2022-11-11
Deposit 150nm Al2O3 on either:
Deposit ~3nm SiO2, in situ (same machine as above) This improves adhesion to photoresist.
Lithography - your preferred method
Etch the Al2O3 in Panasonic ICP 1/2 Use 50W version. Overetch by ~20%, will also etch through the thin SiO2 layer.
Strip PR - either in situ, or via NMP 80°C soak followed by PEii Technics ashing. In situ PR strip appears to give better + faster results.
If pieces of the wafer are at risk of falling into the chamber, mount the product wafer to a carrier wafer:

Logitech Wax Mounting Recipe - Bulk Crystal Bond


If you are only etching small holes through the wafer (majority of wafer is intact), then wax-mounting is not necessary.

Critical - Ensure no wax is present on either side or edge of wafer prior to DSE etching, or wafer may break in the DSE during robot unload!
Use POLOS spinners with ACE/ISO to clean front and back of wafer. This also removes any excess wax if you wax-mounted your wafer.
DSEiii etch - reduce Dep step to eliminate grassing:
  • Bosch Cycles: Dep: 1.2sec / Etch A: 1.5sec / Etch B: 2.0sec
  • Rate ≈ 4.25µm / min
Can use Lasermonitor and/or Camera to observe when etch is fully through. Trenches may get black/rough, but then clear up when fully etched.

Record Helium FLOW during recipe run, for next step (if He leaks).

If you did not wax-mount your wafer, the recipe will eventually fail for Helium Pressure/Flow our of compliance. This is because the cooling Helium leaks through the wafer when the openings get fully etched through.

Once this happens,

  • Leave your wafer in the chamber, then
  • Edit recipe to set Helium Cooling (first step only) to "Flow Control Only". Choose typical flow form normal process from above (Something like ~6sccm? Not sure.)
Strip Al2O3/SiO2 either with HF, or same Pan1/2 dry etch as above.
IF wax-mounted - either
  • dissolve in Acetone overnight (make sure to excess-fill enough and cover tightly with tinfoil so it doesn't dry up), complete with ACE/ISO rinse

OR

  • place wafer on tinfoil-covered hotplate at 150°C, and slide product wafer off, then
    • ACE/ISO clean to remove wax.

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

PlasmaTherm/SLR Fluorine Etcher

Process Control Data (Fluorine ICP Etcher)

Si Etching (Fluorine ICP Etcher)

  • SiVertHF - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
    • Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
    • 89-90 degree etch angle, ie, vertical.
    • Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed in situ before the Si etch.
    • High selectivity to Al2O3 masks.
      • For high aspect ratio Si etching, try ALD Al2O3 (~20-30nm) + SiO2 (2nm, for PR adhesion) hardmasks followed by Pan2 Al2O3 etch (will go straight through the thin SiO2 without additional etch time). Works well for allowing thin PR's (eg. DUV or EBL PR's) to enable deep etches.

SiO2 Etching (Fluorine ICP Etcher)

  • SiO2 Etching using Ruthenium Hardmask - Full Process Traveler
    • Ning Cao & Bill Mitchell, 2019-06
    • High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.
    • Etch also works well with PR masking
    • Chemistry: CHF3/CF4
    • Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.
    • Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
    • 50W Bias:
      • Selectivity to photoresist: 1.10–1.20
      • SiO2 selectivity to Ru: 36
      • SiO2 etch rate: 263nm/min
    • 200W Bias:
      • SiO2 selectivity to Ru: 38
      • SiO2 etch rate: 471nm/min
    • This etch is detailed in the following article: W.J. Mitchell et al., JVST-A, May 2021

Photoresist & ARC (Fluorine ICP Etcher)

Chain multiple Recipes in a Flow, to allow you to to do in situ BARC etching, and follow up with in situ Photoresist Strip.

PR/BARC Etch (Fluorine ICP Etcher)

  • Etching DUV42P-6 Bottom Anti-Reflection Coating
    • ~60nm thick (2500krpm)
    • O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
    • 1min

Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)

    • O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
    • 75W Bias can be helpful for difficult to remove polymers, eg. 2min
    • Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

Cleaning Procedures (Fluorine ICP Etcher)

To Be Added

ICP Etch 1 (Panasonic E626I)

Process Control Data (Panasonic 1)

SiO2 Etching (Panasonic 1)

Recipes

Recipe Variations

Use these to determine how each etch parameter affects the process.

SiNx Etching (Panasonic 1)

Al Etch (Panasonic 1)

Cr Etch (Panasonic 1)

Ta Etch (Panasonic 1)

Ti Etch (Panasonic 1)

W-TiW Etch (Panasonic 1)

GaAs-AlGaAs Etch (Panasonic 1)

GaN Etch (Panasonic 1)

Photoresist and ARC Etching (Panasonic 1)

Please see the recipes for Panasonic ICP#2 - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

SiC Etch (Panasonic 1)

Sapphire Etch (Panasonic 1)

Old Deleted Recipes

Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the tool's Supervisor and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

ICP Etch 2 (Panasonic E640)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

Process Control Data (Panasonic 2)

SiO2 Etching (Panasonic 2)

Recipes

Recipe Variations

Use these to determine how etch parameters affect the process.

SiNx Etching (Panasonic 2)

Al Etch (Panasonic 2)

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry (click for plots of etch rate)

Contributed by Brian Markman, 2018

  • BCl3 = 30sccm
  • Pressure = 0.50 Pa
  • ICP Source RF = 500
  • Bias RF = 50W or 250W (250W can burn PR)
  • Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
  • Etch Rate 50W: 39.6nm/min (0.66nm/sec)
  • Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

GaAs Etch (Panasonic 2)

Photoresist and ARC etching (Panasonic 2)

Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

ARC Etching: DUV-42P or AR6 (Panasonic 2)

  • O2 = 40 sccm // 0.5 Pa
  • ICP = 75W // RF = 75W
  • 45 sec for full etching (incl. overetch) of ~60nm DUV-42P (same as for AR6; 2018-2019, Demis/BrianT)

Photoresist Etch/Strip (Panasonic 2)

Works very well for photoresist stripping

  • O2 = 40 sccm // 1.0 Pa
  • ICP = 350W // RF = 100W
  • Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, Demis)
  • 2m30sec to fully remove UV6-0.8 with ~200% overetch (2019, Demis)

Ru (Ruthenium) Etch (Panasonic 2)

ICP-Etch (Unaxis VLR)

Process Control Data (Unaxis VLR)

GaAs-AlGaAs Etch (Unaxis VLR)

InP-InGaAs-InAlAs Etch (Unaxis VLR)

GaN Etch (Unaxis VLR)

GaSb Etch (Unaxis VLR)

Available - ask staff

Cleaning Recipes (Unaxis VLR)

To Be Added: Required cleaning time & recipes

Oxford ICP Etcher (PlasmaPro 100 Cobra)

Process Control Data (Oxford ICP Etcher)

Process Control Data for "Std InP Ridge Etch" - Calibration / Process testing data taken using the "InP Ridge Etch" process (Cl2/CH4/H2 @ 60°C, SiO2 Hardmask)

InP Ridge Etch (Oxford ICP Etcher)

Low-Temp (60°C) Process

  • Low-Temp InP Ridge Etch Characterization - Ning Cao, 2021-09-08
    • InP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
    • Recipe: Cl2/CH4/H2 - 60°C
    • NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
  • See Operating Procedure for full traveler and post-cleaning.

InP Grating Etch (Oxford ICP Etcher)

  • InP/InGaAsP Grating Etch Characterization - Ning Cao, 2021-08-26
    • InP/InGaAsP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
    • Recipe: Cl2/CH4/H2/Ar - 20°C
    • NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
  • See Operating Procedure for full traveler and post-cleaning.

GaAs Etch (Oxford ICP Etcher)

This recipe also provides a starting point for GaSb-based etches.

  • GaAs-based materials - etch recipe available on tool - provided by Oxford, not yet qualified internally
  • See Operating Procedure for full traveler and post-cleaning.

GaN Etch (Oxford ICP Etcher)

  • GaN-based materials - etch recipe available on tool - provided by Oxford, not yet qualified internally
  • See Operating Procedure for full traveler and post-cleaning.

GaN Atomic Layer Etching (Oxford ICP Etcher)

GaN-ALE Recipe written and tested by users - contact supervisor for use.

Si Deep RIE (PlasmaTherm/Bosch Etch)

This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!
The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
For Deep Silicon Etching, the Plasma-Therm DSE-iii is often used.  Some single-step Silicon etching is still performed on the SLR Fluorine ICP, due to the slower etch rate.

Bosch and Release Etch (Si Deep RIE)

  • Bosch and Release Processes
    • Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
    • Etch rate depends on area of exposed silicon being etched.
    • Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
    • SiO2 (PECVD) mask has ~100:1 selectivity
    • Thermal SiO2 has ~300:1 selectivity.

Single-step Si Etching (not Bosch Process!) (Si Deep RIE)