Difference between revisions of "ICP Etching Recipes"

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(→‎InP Ridge Etch (Oxford ICP Etcher): links to PDFs of etch characterizations)
m (Renaming Process Control Data)
 
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=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=
 
=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=
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==Process Control Data (DSEIII)==
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 +
*'''''[[To Be Added]]'''''
  
 
==Edge-Bead Removal==
 
==Edge-Bead Removal==
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=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=
 
=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=
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==Process Control Data (Fluorine ICP Etcher)==
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*[[Test Data of Etching SiO2 with CHF3/CF4-Fluorine ICP Etcher|SiO<sub>2</sub> Etching with CHF3/CF4 (FL-ICP]])
 +
 
==Si Etching (Fluorine ICP Etcher)==
 
==Si Etching (Fluorine ICP Etcher)==
  
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**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
 
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
  
==Historical Data (Fluorine ICP Etcher)==
+
==Cleaning Procedures (Fluorine ICP Etcher)==
 +
''To Be Added''
  
===SiO2 Etch Historical Data===
+
=[[ICP Etch 1 (Panasonic E626I)]]=
  
*[[Test Data of Etching SiO2 with CHF3/CF4-Fluorine ICP Etcher|Test Data of Etching SiO<sub>2</sub> with CHF3/CF4-Fluorine ICP Etcher]]
+
==Process Control Data (Panasonic 1)==
  
==Cleaning Procedures (Fluorine ICP Etcher)==
+
*[[Test Data of etching SiO2 with CHF3/CF4-ICP1|SiO<sub>2</sub> Etch with CHF<sub>3</sub>/CF<sub>4</sub> - Process Control Data]]
''To Be Added''
 
  
=[[ICP Etch 1 (Panasonic E626I)]]=
 
 
==SiO<sub>2</sub> Etching (Panasonic 1)==
 
==SiO<sub>2</sub> Etching (Panasonic 1)==
  
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**Etch rate ≈ 2300Å/min (users must calibrate)
 
**Etch rate ≈ 2300Å/min (users must calibrate)
 
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)
 
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)
 
===Historical Data (SiO2, Panasonic 1)===
 
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Florine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
 
*[[Test Data of etching SiO2 with CHF3/CF4-ICP1|Test Data of etching SiO2 with CHF3/CF4]]
 
  
 
===Recipe Variations===
 
===Recipe Variations===
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Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.
 
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.
  
If you need to free up a recipe slot, please contact [[Don Freeborn|Don]] and he'll help you find an old recipe to replace.  We take photographs of old recipes, and save them in case a group needs to revive the recipe.  Contact us if your old recipe went missing.
+
If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace.  We take photographs of old recipes, and save them in case a group needs to revive the recipe.  Contact us if your old recipe went missing.
  
 
=[[ICP Etch 2 (Panasonic E640)]]=
 
=[[ICP Etch 2 (Panasonic E640)]]=
 
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files.  The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.
 
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files.  The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.
 +
 +
==Process Control Data (Panasonic 2)==
 +
 +
*[[Test Data of etching SiO2 with CHF3/CF4|SiO2 Etch with CHF3/CF4 - Process Control Data]]
  
 
==SiO<sub>2</sub> Etching (Panasonic 2)==
 
==SiO<sub>2</sub> Etching (Panasonic 2)==
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*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]
 
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]
 
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]
 
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]
 
===Historical Data (SiO2 Etch, Panasonic 2)===
 
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Fluorine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
 
*[[Test Data of etching SiO2 with CHF3/CF4]]
 
  
 
===Recipe Variations===
 
===Recipe Variations===
''Use these to determine how each etch parameter affects the process.''
+
''Use these to determine how etch parameters affect the process.''
  
*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipe]
+
*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]
  
 
==SiN<sub>x</sub> Etching (Panasonic 2)==
 
==SiN<sub>x</sub> Etching (Panasonic 2)==
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=[[ICP-Etch (Unaxis VLR)]]=
 
=[[ICP-Etch (Unaxis VLR)]]=
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==Process Control Data (Unaxis VLR)==
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*[[Unaxis VLR Etch - Process Control Data|InP Etch - Process Control Data]]
 +
 
==GaAs-AlGaAs Etch (Unaxis VLR)==
 
==GaAs-AlGaAs Etch (Unaxis VLR)==
  
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=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=
 
=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=
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==Process Control Data (Oxford ICP Etcher)==
 +
[[Oxford ICP Etcher - Process Control Data|Process Control Data for "Std InP Ridge Etch"]] - ''Calibration / Process testing data taken using the "InP Ridge Etch" process (Cl2/CH4/H2 @ 60°C, SiO<sub>2</sub> Hardmask)''
  
 
==InP Ridge Etch (Oxford ICP Etcher)==
 
==InP Ridge Etch (Oxford ICP Etcher)==
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*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
 
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
 
**Bulk InP etches, no mounting adhesive, pieces on blank Silicon carrier
 
**Bulk InP etches, no mounting adhesive, pieces on blank Silicon carrier
 +
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
 
*[[Oxford Etcher - InP Ridge Etch Traveler|InP Ridge Process - Basic Traveler]]
 
*[[Oxford Etcher - InP Ridge Etch Traveler|InP Ridge Process - Basic Traveler]]
  
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*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
 
*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
 +
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
 
*[[Oxford Etcher - InP//InGaAsP Grating Traveler|InP//InGaAsP Grating - Basic Traveler]]
 
*[[Oxford Etcher - InP//InGaAsP Grating Traveler|InP//InGaAsP Grating - Basic Traveler]]
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 +
==GaAs Etch (Oxford ICP Etcher)==
 +
This recipe also provides a starting point for GaSb-based etches.
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*[[Oxford Etcher - GaAs Etch Recipe|GaAs-based materials - etch recipe]] - ''provided by Oxford, not yet qualified internally''
 +
*[[Oxford Etcher - GaAs-based Materials - Basic Traveler|GaAs-based Materials - Basic Traveler]]
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==GaN Etch (Oxford ICP Etcher)==
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 +
*[[Oxford Etcher - GaN Etch Recipe|GaN-based materials - etch recipe]] - ''provided by Oxford, not yet qualified internally''
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*[[Oxford Etcher - GaN-based Materials - Basic Traveler|GaN-based Materials - Basic Traveler]]
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==GaN Atomic Layer Etching (Oxford ICP Etcher)==
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''GaN-ALE Recipe written but still undergoing testing - contact [[Tony Bosch|supervisor]] for use.''
  
 
=[[Si Deep RIE (PlasmaTherm/Bosch Etch)]]=
 
=[[Si Deep RIE (PlasmaTherm/Bosch Etch)]]=
 
  '''This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!'''
 
  '''This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!'''
 
  The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
 
  The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
  For Deep Silicon Etching, the Plasma-Therm DSE-iii is often used.  Some single-step Silicon etching is still performed on the SLR Fluorine ICP, due to the slower etch rate.
+
  For Deep Silicon Etching, the [[ICP Etching Recipes#High Rate Bosch Etch .28DSEIII.29|Plasma-Therm DSE-iii]] is often used.  Some single-step Silicon etching is still performed on the [[ICP Etching Recipes#Si Etching .28Fluorine ICP Etcher.29|SLR Fluorine ICP]], due to the slower etch rate.
  
 
==Bosch and Release Etch (Si Deep RIE)==
 
==Bosch and Release Etch (Si Deep RIE)==

Latest revision as of 17:27, 10 May 2022

Back to Dry Etching Recipes.

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

Process Control Data (DSEIII)

Edge-Bead Removal

Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

High Rate Bosch Etch (DSEIII)

  • Bosch Process Recipe and Characterization - Standard recipe on the tool.
    • Recipe Name: "Plasma-Therm Standard DSE" (Production - copy to your Personal category)
    • Standard Bosch Process for high aspect-ratio, high-selectivity Silicon etching.
    • Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
      • To reduce roughening/grassing (black silicon), reduce Dep step time by ~20%.
    • Patterns with different etched areas will have different "optimal" parameters.
    • Approx Selectivity to Photoresist: 60-80 or better. Larger open area, lower selectivity and lower etch rate.

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

PlasmaTherm/SLR Fluorine Etcher

Process Control Data (Fluorine ICP Etcher)

Si Etching (Fluorine ICP Etcher)

  • SiVertHF - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
    • Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
    • 89-90 degree etch angle, ie, vertical.
    • Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed in situ before the Si etch.

SiO2 Etching (Fluorine ICP Etcher)

  • SiO2 Etching using Ruthenium Hardmask - Full Process Traveler
    • Ning Cao & Bill Mitchell, 2019-06
    • High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.
    • Chemistry: CHF3/CF4
    • Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.
    • Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
    • 200W Bias:
      • SiO2 selectivity to Ru: 38
      • SiO2 etch rate: 471nm/min
    • 50W Bias:
      • Higher selectivity to photoresist: TBD
      • SiO2 selectivity to Ru: 36
      • SiO2 etch rate: 263nm/min
    • This etch is detailed in the following article: W.J. Mitchell et al., JVST-A, May 2021

Photoresist & ARC (Fluorine ICP Etcher)

Chain multiple Recipes in a Flow, to allow you to to do in situ BARC etching, and follow up with in situ Photoresist Strip.

PR/BARC Etch (Fluorine ICP Etcher)

  • Etching DUV42P-6 Bottom Anti-Reflection Coating
    • ~60nm thick (2500krpm)
    • O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
    • 1min

Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)

    • O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
    • Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

Cleaning Procedures (Fluorine ICP Etcher)

To Be Added

ICP Etch 1 (Panasonic E626I)

Process Control Data (Panasonic 1)

SiO2 Etching (Panasonic 1)

Recipes

Recipe Variations

Use these to determine how each etch parameter affects the process.

SiNx Etching (Panasonic 1)

Al Etch (Panasonic 1)

Cr Etch (Panasonic 1)

Ta Etch (Panasonic 1)

Ti Etch (Panasonic 1)

W-TiW Etch (Panasonic 1)

GaAs-AlGaAs Etch (Panasonic 1)

GaN Etch (Panasonic 1)

Photoresist and ARC Etching (Panasonic 1)

Please see the recipes for Panasonic ICP#2 - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

SiC Etch (Panasonic 1)

Sapphire Etch (Panasonic 1)

Old Deleted Recipes

Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the tool's Supervisor and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

ICP Etch 2 (Panasonic E640)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

Process Control Data (Panasonic 2)

SiO2 Etching (Panasonic 2)

Recipes

Recipe Variations

Use these to determine how etch parameters affect the process.

SiNx Etching (Panasonic 2)

Al Etch (Panasonic 2)

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry (click for plots of etch rate)

Contributed by Brian Markman, 2018

  • BCl3 = 30sccm
  • Pressure = 0.50 Pa
  • ICP Source RF = 500
  • Bias RF = 50W or 250W (250W can burn PR)
  • Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
  • Etch Rate 50W: 0.66nm/sec
  • Etch Rate 250W: 1.0 nm/sec

GaAs Etch (Panasonic 2)

Photoresist and ARC etching (Panasonic 2)

Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

ARC Etching: DUV-42P or AR6

  • O2 = 40 sccm // 0.5 Pa
  • ICP = 75W // RF = 75W
  • 45 sec for full etching of DUV-42P (same as for AR6; 2018-2019, Demis/BrianT)

UV6-0.8 Etching

Works very well for photoresist stripping

  • O2 = 40 sccm // 1.0 Pa
  • ICP = 350W // RF = 100W
  • Etch Rate = 518.5nm / 1min (2019, Demis)
  • 2m30sec to fully remove with ~200% overetch

Ru (Ruthenium) Etch (Panasonic 2)

ICP-Etch (Unaxis VLR)

Process Control Data (Unaxis VLR)

GaAs-AlGaAs Etch (Unaxis VLR)

InP-InGaAs-InAlAs Etch (Unaxis VLR)

GaN Etch (Unaxis VLR)

GaSb Etch (Unaxis VLR)

Oxford ICP Etcher (PlasmaPro 100 Cobra)

Process Control Data (Oxford ICP Etcher)

Process Control Data for "Std InP Ridge Etch" - Calibration / Process testing data taken using the "InP Ridge Etch" process (Cl2/CH4/H2 @ 60°C, SiO2 Hardmask)

InP Ridge Etch (Oxford ICP Etcher)

InP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).

Low-Temp (60°C) Process

InP Grating Etch (Oxford ICP Etcher)

InP/InGaAsP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).

GaAs Etch (Oxford ICP Etcher)

This recipe also provides a starting point for GaSb-based etches.

GaN Etch (Oxford ICP Etcher)

GaN Atomic Layer Etching (Oxford ICP Etcher)

GaN-ALE Recipe written but still undergoing testing - contact supervisor for use.

Si Deep RIE (PlasmaTherm/Bosch Etch)

This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!
The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
For Deep Silicon Etching, the Plasma-Therm DSE-iii is often used.  Some single-step Silicon etching is still performed on the SLR Fluorine ICP, due to the slower etch rate.

Bosch and Release Etch (Si Deep RIE)

  • Bosch and Release Processes
    • Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
    • Etch rate depends on area of exposed silicon being etched.
    • Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
    • SiO2 (PECVD) mask has ~100:1 selectivity
    • Thermal SiO2 has ~300:1 selectivity.

Single-step Si Etching (not Bosch Process!) (Si Deep RIE)