Difference between revisions of "ICP Etching Recipes"

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{{recipes|Dry Etching}}
 
{{recipes|Dry Etching}}
=[[XeF2 Etch (Xetch)]]=
 
*[[media:06-XeF2-etch-recipe.pdf|Si Etch Recipe]]
 
  
 +
=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=
  
 +
==Process Control Data (DSEIII)==
  
 +
*'''''[[To Be Added]]'''''
  
 +
==Edge-Bead Removal==
 +
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!
 +
 +
*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
 +
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
 +
 +
==High Rate Bosch Etch (DSEIII)==
 +
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.
 +
**Recipe Name: "'''''Plasma-Therm Standard DSE'''''" (''Production'' - copy to your ''Personal'' category)
 +
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
 +
**Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
 +
***To reduce roughening/grassing (black silicon), reduce Dep step time by ~20%.
 +
**Patterns with different etched areas will have different "optimal" parameters.
 +
**Approx Selectivity to Photoresist: 60-80 or better.  Larger open area, lower selectivity and lower etch rate.
 +
 +
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==
 +
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
 +
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
 +
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
 +
**Lower selectivity, lower etch rate, smoother sidewalls.
 +
 +
=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=
 +
 +
==Process Control Data (Fluorine ICP Etcher)==
 +
 +
*[[Test Data of Etching SiO2 with CHF3/CF4-Fluorine ICP Etcher|SiO<sub>2</sub> Etching with CHF3/CF4 (FL-ICP]])
 +
 +
==Si Etching (Fluorine ICP Etcher)==
 +
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C<sub>4</sub>F<sub>8</sub>/SF<sub>6</sub>/CF<sub>4</sub> and resist mask
 +
**Etch Rates: Si ≈ 300-350 nm/min; SiO<sub>2</sub> ≈ 30-35 nm/min
 +
**89-90 degree etch angle, ie, vertical.
 +
**Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO<sub>2</sub> etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
 +
 +
==SiO2 Etching (Fluorine ICP Etcher)==
 +
 +
*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
 +
**''Ning Cao & Bill Mitchell, 2019-06''
 +
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
 +
**''Etch also works well with PR masking''
 +
**''Chemistry: CHF3/CF4''
 +
**''Variations in SiO<sub>2</sub> etch Bias Power: 50 / 200 / 400W bias.''
 +
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
 +
**50W Bias:
 +
***Selectivity to photoresist: 1.10–1.20
 +
***SiO<sub>2</sub> selectivity to Ru: 36
 +
***SiO<sub>2</sub> etch rate: 263nm/min
 +
**200W Bias:
 +
***SiO<sub>2</sub> selectivity to Ru: 38
 +
***SiO<sub>2</sub> etch rate: 471nm/min
 +
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
 +
 +
==Photoresist & ARC (Fluorine ICP Etcher)==
 +
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.
 +
 +
===PR/BARC Etch (Fluorine ICP Etcher)===
 +
 +
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
 +
**~60nm thick (2500krpm)
 +
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
 +
**1min
 +
 +
===Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)===
 +
 +
**O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
 +
**75W Bias can be helpful for difficult to remove polymers, eg. 2min
 +
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
 +
 +
==Cleaning Procedures (Fluorine ICP Etcher)==
 +
''To Be Added''
  
{{recipes|Dry Etching}}
 
 
=[[ICP Etch 1 (Panasonic E626I)]]=
 
=[[ICP Etch 1 (Panasonic E626I)]]=
 +
 +
==Process Control Data (Panasonic 1)==
 +
 +
*[[Test Data of etching SiO2 with CHF3/CF4-ICP1|SiO<sub>2</sub> Etch with CHF<sub>3</sub>/CF<sub>4</sub> - Process Control Data]]
 +
 
==SiO<sub>2</sub> Etching (Panasonic 1)==
 
==SiO<sub>2</sub> Etching (Panasonic 1)==
*[[media:Panasonic1-SiO-Etch.pdf|SiO<sub>2</sub> Vertical Etch Recipe]]
+
 
*[[media:Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf|SiO<sub>2</sub> CHF3 Etch Variations]]
+
===Recipes===
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO<sub>2</sub> Vertical Etch Recipe Parameters - CHF<sub>3</sub> "SiOVert"]
 +
**Etch rate ≈ 2300Å/min (users must calibrate)
 +
**Selectivity (SiO2:Photoresist) ≈ greater than 1:1 (users must calibrate)
 +
 
 +
===Recipe Variations===
 +
''Use these to determine how each etch parameter affects the process.''
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO<sub>2</sub> CHF<sub>3</sub> Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching
 +
 
 +
==SiN<sub>x</sub> Etching (Panasonic 1)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/c/ce/Panasonic1-SiN-Etch-Plasma-CF4-O2-ICP-revA.pdf SiN<sub>x</sub> Etch Rates and Variations - CF<sub>4</sub>-O<sub>2</sub>]
 +
 
 +
==Al Etch (Panasonic 1)==
 +
 
 +
*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - Cl<sub>2</sub>BCl<sub>3</sub>]
 +
*[https://wiki.nanotech.ucsb.edu/wiki/images/6/60/32-Reducing_AlCl3_Corrosion_with_CHF3_plasma.pdf AlCl<sub>3</sub> Erosion Issue and the Solution]
  
 
==Cr Etch (Panasonic 1)==
 
==Cr Etch (Panasonic 1)==
*[[media:Panasonic-1-Cr-Etch-revA.pdf|Cr Etch Recipes]]
+
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/8/88/Panasonic-1-Cr-Etch-revA.pdf Cr Etch Recipes - Cl<sub>2</sub>O<sub>2</sub>]
 +
 
 +
==Ta Etch (Panasonic 1)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/f/f2/104_Ta_Etch.pdf Ta Etch Recipe] - Cl2/BCl3
 +
 
 +
==Ti Etch (Panasonic 1)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/4/47/Panasonic-1-Ti-Etch-Deep-RevA.pdf Ti Deep Etch Recipes - Cl<sub>2</sub>Ar]
 +
**See [[doi:10.1149/1.2006647|E. Parker, ''et. al.'' Jnl. Electrochem. Soc., 152 (10) C675-C683 2005]].
 +
 
 +
==W-TiW Etch (Panasonic 1)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/7/76/Panasonic1-TiW-W-Etch-Plasma-RIE-RevA.pdf Ti-TiW Etch Recipes - SF<sub>6</sub>Ar]
 +
 
 +
==GaAs-AlGaAs Etch (Panasonic 1)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/b/bb/Panasonic1-GaAs-PhotonicCrystal-RIE-Plasma-Nanoscale-Etch-RevA.pdf GaAs-Nanoscale Etch Recipe - PR mask - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar]
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/2/26/12-Plasma_Etching_of_AlGaAs-Panasonic_ICP-1-Etcher.pdf AlGaAs Etch Recipes - Cl<sub>2</sub>N<sub>2</sub>]
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/0/04/Panasonic1-GaAs-Via-Etch-Plasma-RIE-Fast-DRIE-RevA.pdf GaAs DRIE via Etch Recipes - Cl<sub>2</sub>-BCl<sub>3</sub>-Ar PR passivation]
  
 
==GaN Etch (Panasonic 1)==
 
==GaN Etch (Panasonic 1)==
*[[media:07-GaN_Etch-Panasonic-ICP-1.pdf|GaN Etch Recipes]]
+
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d6/07-GaN_Etch-Panasonic-ICP-1.pdf GaN Etch Recipes Cl<sub>2</sub>N<sub>2</sub>]
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl<sub>3</sub>-SF<sub>6</sub>]
 +
 
 +
==Photoresist and ARC Etching (Panasonic 1)==
 +
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.
 +
 
 +
Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.
 +
 
 +
==SiC Etch (Panasonic 1)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d0/Panasonic_1-SiC-ICP-RIE-Etch-Plasma-SF6-RevA.pdf SiC Etch Recipes Ni Mask - SF<sub>6</sub>]
 +
 
 +
==Sapphire Etch (Panasonic 1)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/3/3a/Panasonic1-sapphire-etch-RIE-Plasma-BCl3-ICP-RevA.pdf Sapphire Etch Recipes Ni and PR Mask - BCl<sub>3</sub>-Cl<sub>2</sub>]
 +
 
 +
==Old Deleted Recipes==
 +
Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.
 +
 
 +
If you need to free up a recipe slot, please contact the [[ICP Etch 1 (Panasonic E626I)|tool's Supervisor]] and they'll help you find an old recipe to replace.  We take photographs of old recipes, and save them in case a group needs to revive the recipe.  Contact us if your old recipe went missing.
  
 
=[[ICP Etch 2 (Panasonic E640)]]=
 
=[[ICP Etch 2 (Panasonic E640)]]=
 +
Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files.  The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.
 +
 +
==Process Control Data (Panasonic 2)==
 +
 +
*[[Test Data of etching SiO2 with CHF3/CF4|SiO2 Etch with CHF3/CF4 - Process Control Data]]
 +
 
==SiO<sub>2</sub> Etching (Panasonic 2)==
 
==SiO<sub>2</sub> Etching (Panasonic 2)==
*[[media:Panasonic2-SiOx-Recipe.pdf|SiO<sub>2</sub> Vertical Etch Recipe]]
+
 
 +
===Recipes===
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO<sub>2</sub> Vertical Etch Recipe - CHF<sub>3</sub> "SiOVert"]
 +
**Direct copy of "SiOVert" from ICP#1, [[ICP_Etching_Recipes#SiO2_Etching_.28Panasonic_1.29|see parameters there]].
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]
 +
 
 +
===Recipe Variations===
 +
''Use these to determine how etch parameters affect the process.''
 +
 
 +
*[https://wiki.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipes]
 +
 
 +
==SiN<sub>x</sub> Etching (Panasonic 2)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/0/06/Panasonic2-ICP-Plasma-Etch-SiN-nanoscale-rev1.pdf SiN<sub>x</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]
 +
 
 +
==Al Etch (Panasonic 2)==
 +
 
 +
*[https://wiki.nanotech.ucsb.edu/wiki/images/3/3b/Panasonic-1-Al-Etch-RevA.pdf Al Etch Recipes - use panasonic 1 parameters, etch rate 50% higher]
 +
 
 +
==Al2O3 Etching (Panasonic 2)==
 +
[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/Brian_Markman_-_Al2O3_ICP2_Etch_Rates_2018.pdf ALD Al2O3 Etch Rates in BCl3 Chemistry] (click for plots of etch rate)
 +
 
 +
''Contributed by Brian Markman, 2018''
 +
 
 +
*BCl3 = 30sccm
 +
*Pressure = 0.50 Pa
 +
*ICP Source RF = 500
 +
*Bias RF = 50W or 250W (250W can burn PR)
 +
*Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
 +
*Etch Rate 50W: 39.6nm/min (0.66nm/sec)
 +
*Etch Rate 250W: 60.0nm/min (1.0 nm/sec)
 +
 
 +
==GaAs Etch (Panasonic 2)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl<sub>2</sub>N<sub>2</sub>]
 +
 
 +
==Photoresist and ARC etching (Panasonic 2)==
 +
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:
 +
 
 +
===ARC Etching: DUV-42P or AR6 (Panasonic 2)===
 +
 
 +
*O2 = 40 sccm // 0.5 Pa
 +
*ICP = 75W // RF = 75W
 +
*45 sec for full etching of DUV-42P (same as for AR6; 2018-2019, [[Demis D. John|Demis]]/[[Brian Thibeault|BrianT]])
 +
 
 +
===Photoresist Etch/Strip (Panasonic 2)===
 +
Works very well for photoresist stripping
 +
 
 +
*O2 = 40 sccm // 1.0 Pa
 +
*ICP = 350W // RF = 100W
 +
*Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, [[Demis D. John|Demis]])
 +
*2m30sec to fully remove UV6-0.8 with ~200% overetch
 +
 
 +
==Ru (Ruthenium) Etch (Panasonic 2)==
 +
 
 +
*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
 +
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]
  
 
=[[ICP-Etch (Unaxis VLR)]]=
 
=[[ICP-Etch (Unaxis VLR)]]=
==InP Etch (Unaxis VLR)==
+
 
===InP Etch ===
+
==Process Control Data (Unaxis VLR)==
*[[media:UNAXIS-VLR-InP-Etch-200C-Recipe.pdf|InP Etch Recipe (200C)]]
+
 
===InP Etch (H<sub>2</sub> Ar)===
+
*[[Unaxis VLR Etch - Process Control Data|InP Etch - Process Control Data]]
*[[media:UNAXIS-VLR-InP-Etch-Ar-200C-Recipe.pdf|InP Etch Recipe (H<sub>2</sub> Ar 200C)]]
+
 
 +
==GaAs-AlGaAs Etch (Unaxis VLR)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4e/15-GaAs_etch-Unaxis_ICP_etcher.pdf GaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/1/1f/14-AlAs-GR-cal_etch-Unaxis_ICP_etcher.pdf AlGaAs Etch Recipe (Cl<sub>2</sub>N<sub>2</sub> 30C)]
 +
 
 +
==InP-InGaAs-InAlAs Etch (Unaxis VLR)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/9/90/18-InP-based_etching-Cl2N2Ar.pdf InP-based Material Etch Profile (Cl<sub>2</sub>N<sub>2</sub>Ar200C)]
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/a/ad/17-InP%26InGaAs_etch-Cl2H2Ar-Unaxis-VLR.pdf InP-InGaAs Etch Profile (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)]
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/6/6e/SiO2-Mask_Etch_Recipe_for_Unaxis_Cl2_Etch.pdf Recipe of Etching SiO<sub>2</sub> Mask for Cl<sub>2</sub> Etch (ICP#2)]
 +
*[[InP Etch Test Result in Details|InP Etch Historical Data (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)]]
 +
*[[InP Etch Rate and Selectivity (InP/SiO2)|InP Etch Test]]
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/a/ac/Lower-Etch-Rate_InP_Etch_using_Unaxis_PM1_tool_at_200_C.pdf Lower etch-rate InP Etch (Cl<sub>2</sub>N<sub>2</sub> 200C)]
 +
 
 +
==GaN Etch (Unaxis VLR)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/d/df/09-Plasma_Etching_of_GaN-UnaxisPM1.pdf GaN Etch Recipe (Cl<sub>2</sub>BCl<sub>3</sub>N<sub>2</sub>Ar 85C)]
 +
 
 +
==GaSb Etch (Unaxis VLR)==
 +
''Available - ask staff''
 +
 
 +
== Cleaning Recipes (Unaxis VLR) ==
 +
''To Be Added: Required cleaning time & recipes''
 +
 
 +
=[[Oxford ICP Etcher (PlasmaPro 100 Cobra)]]=
 +
 
 +
==Process Control Data (Oxford ICP Etcher)==
 +
[[Oxford ICP Etcher - Process Control Data|Process Control Data for "Std InP Ridge Etch"]] - ''Calibration / Process testing data taken using the "InP Ridge Etch" process (Cl2/CH4/H2 @ 60°C, SiO<sub>2</sub> Hardmask)''
 +
 
 +
==InP Ridge Etch (Oxford ICP Etcher)==
 +
===Low-Temp (60°C) Process===
 +
 
 +
*[[Media:Oxford Etcher - InP Ridge Etch using Oxford PlasmaPro 100 Cobra - 2021-09-08.pdf|Low-Temp InP Ridge Etch Characterization]] - ''Ning Cao, 2021-09-08''
 +
**InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
 +
**Recipe: Cl2/CH4/H2 - 60°C
 +
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
 +
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.
 +
 
 +
==InP Grating Etch (Oxford ICP Etcher)==
 +
 
 +
*[[Media:Oxford Etcher - InP Grating Etch at 20 C - Oxford Cobra 300 2021-08-26.pdf|InP/InGaAsP Grating Etch Characterization]] - ''Ning Cao, 2021-08-26''
 +
**InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
 +
**Recipe: Cl2/CH4/H2/Ar - 20°C
 +
**NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
 +
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.
 +
 
 +
==GaAs Etch (Oxford ICP Etcher)==
 +
This recipe also provides a starting point for '''GaSb'''-based etches.
 +
 
 +
*GaAs-based materials - etch recipe available on tool - ''provided by Oxford, not yet qualified internally''
 +
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.
 +
 
 +
==GaN Etch (Oxford ICP Etcher)==
 +
 
 +
*GaN-based materials - etch recipe available on tool - ''provided by Oxford, not yet qualified internally''
 +
*See [[Oxford ICP Etcher (PlasmaPro 100 Cobra)#Documentation|Operating Procedure]] for full traveler and post-cleaning.
 +
 
 +
==GaN Atomic Layer Etching (Oxford ICP Etcher)==
 +
''GaN-ALE Recipe written and tested by users - contact [[Tony Bosch|supervisor]] for use.''
 +
 
 +
=[[Si Deep RIE (PlasmaTherm/Bosch Etch)]]=
 +
'''This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!'''
 +
The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
 +
For Deep Silicon Etching, the [[ICP Etching Recipes#High Rate Bosch Etch .28DSEIII.29|Plasma-Therm DSE-iii]] is often used.  Some single-step Silicon etching is still performed on the [[ICP Etching Recipes#Si Etching .28Fluorine ICP Etcher.29|SLR Fluorine ICP]], due to the slower etch rate.
 +
 
 +
==Bosch and Release Etch (Si Deep RIE)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/0/02/10-Si_Etch_Bosch_Release_DRIE.pdf Bosch and Release Processes]
 +
**Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
 +
**Etch rate depends on area of exposed silicon being etched.
 +
**Al<sub>2</sub>O<sub>3</sub> mask (ALD or Sputter) has >9000:1 selectivity
 +
**SiO<sub>2</sub> (PECVD) mask has ~100:1 selectivity
 +
**Thermal SiO<sub>2</sub> has ~300:1 selectivity.
 +
 
 +
==Single-step Si Etching (not Bosch Process!) (Si Deep RIE)==
 +
 
 +
*[//wiki.nanotech.ucsb.edu/wiki/images/d/d2/10-Si_Etch_using_DRIE_%28single-step%29.pdf Single-step Si Vertical Etch Recipe - SF<sub>6</sub>-C<sub>4</sub>F<sub>8</sub>-Ar]

Revision as of 15:33, 29 September 2022

Back to Dry Etching Recipes.

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

Process Control Data (DSEIII)

Edge-Bead Removal

Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

High Rate Bosch Etch (DSEIII)

  • Bosch Process Recipe and Characterization - Standard recipe on the tool.
    • Recipe Name: "Plasma-Therm Standard DSE" (Production - copy to your Personal category)
    • Standard Bosch Process for high aspect-ratio, high-selectivity Silicon etching.
    • Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
      • To reduce roughening/grassing (black silicon), reduce Dep step time by ~20%.
    • Patterns with different etched areas will have different "optimal" parameters.
    • Approx Selectivity to Photoresist: 60-80 or better. Larger open area, lower selectivity and lower etch rate.

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

PlasmaTherm/SLR Fluorine Etcher

Process Control Data (Fluorine ICP Etcher)

Si Etching (Fluorine ICP Etcher)

  • SiVertHF - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
    • Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
    • 89-90 degree etch angle, ie, vertical.
    • Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed in situ before the Si etch.

SiO2 Etching (Fluorine ICP Etcher)

  • SiO2 Etching using Ruthenium Hardmask - Full Process Traveler
    • Ning Cao & Bill Mitchell, 2019-06
    • High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.
    • Etch also works well with PR masking
    • Chemistry: CHF3/CF4
    • Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.
    • Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
    • 50W Bias:
      • Selectivity to photoresist: 1.10–1.20
      • SiO2 selectivity to Ru: 36
      • SiO2 etch rate: 263nm/min
    • 200W Bias:
      • SiO2 selectivity to Ru: 38
      • SiO2 etch rate: 471nm/min
    • This etch is detailed in the following article: W.J. Mitchell et al., JVST-A, May 2021

Photoresist & ARC (Fluorine ICP Etcher)

Chain multiple Recipes in a Flow, to allow you to to do in situ BARC etching, and follow up with in situ Photoresist Strip.

PR/BARC Etch (Fluorine ICP Etcher)

  • Etching DUV42P-6 Bottom Anti-Reflection Coating
    • ~60nm thick (2500krpm)
    • O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
    • 1min

Photoresist Strip/Polymer Removal (Fluorine ICP Etcher)

    • O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
    • 75W Bias can be helpful for difficult to remove polymers, eg. 2min
    • Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

Cleaning Procedures (Fluorine ICP Etcher)

To Be Added

ICP Etch 1 (Panasonic E626I)

Process Control Data (Panasonic 1)

SiO2 Etching (Panasonic 1)

Recipes

Recipe Variations

Use these to determine how each etch parameter affects the process.

SiNx Etching (Panasonic 1)

Al Etch (Panasonic 1)

Cr Etch (Panasonic 1)

Ta Etch (Panasonic 1)

Ti Etch (Panasonic 1)

W-TiW Etch (Panasonic 1)

GaAs-AlGaAs Etch (Panasonic 1)

GaN Etch (Panasonic 1)

Photoresist and ARC Etching (Panasonic 1)

Please see the recipes for Panasonic ICP#2 - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

SiC Etch (Panasonic 1)

Sapphire Etch (Panasonic 1)

Old Deleted Recipes

Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact the tool's Supervisor and they'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

ICP Etch 2 (Panasonic E640)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

Process Control Data (Panasonic 2)

SiO2 Etching (Panasonic 2)

Recipes

Recipe Variations

Use these to determine how etch parameters affect the process.

SiNx Etching (Panasonic 2)

Al Etch (Panasonic 2)

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry (click for plots of etch rate)

Contributed by Brian Markman, 2018

  • BCl3 = 30sccm
  • Pressure = 0.50 Pa
  • ICP Source RF = 500
  • Bias RF = 50W or 250W (250W can burn PR)
  • Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
  • Etch Rate 50W: 39.6nm/min (0.66nm/sec)
  • Etch Rate 250W: 60.0nm/min (1.0 nm/sec)

GaAs Etch (Panasonic 2)

Photoresist and ARC etching (Panasonic 2)

Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

ARC Etching: DUV-42P or AR6 (Panasonic 2)

  • O2 = 40 sccm // 0.5 Pa
  • ICP = 75W // RF = 75W
  • 45 sec for full etching of DUV-42P (same as for AR6; 2018-2019, Demis/BrianT)

Photoresist Etch/Strip (Panasonic 2)

Works very well for photoresist stripping

  • O2 = 40 sccm // 1.0 Pa
  • ICP = 350W // RF = 100W
  • Etch Rate for UV6-0.8 (DUV PR) = 518.5nm / 1min (2019, Demis)
  • 2m30sec to fully remove UV6-0.8 with ~200% overetch

Ru (Ruthenium) Etch (Panasonic 2)

ICP-Etch (Unaxis VLR)

Process Control Data (Unaxis VLR)

GaAs-AlGaAs Etch (Unaxis VLR)

InP-InGaAs-InAlAs Etch (Unaxis VLR)

GaN Etch (Unaxis VLR)

GaSb Etch (Unaxis VLR)

Available - ask staff

Cleaning Recipes (Unaxis VLR)

To Be Added: Required cleaning time & recipes

Oxford ICP Etcher (PlasmaPro 100 Cobra)

Process Control Data (Oxford ICP Etcher)

Process Control Data for "Std InP Ridge Etch" - Calibration / Process testing data taken using the "InP Ridge Etch" process (Cl2/CH4/H2 @ 60°C, SiO2 Hardmask)

InP Ridge Etch (Oxford ICP Etcher)

Low-Temp (60°C) Process

  • Low-Temp InP Ridge Etch Characterization - Ning Cao, 2021-09-08
    • InP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on blank Silicon carriers (rough side up).
    • Recipe: Cl2/CH4/H2 - 60°C
    • NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
  • See Operating Procedure for full traveler and post-cleaning.

InP Grating Etch (Oxford ICP Etcher)

  • InP/InGaAsP Grating Etch Characterization - Ning Cao, 2021-08-26
    • InP/InGaAsP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
    • Recipe: Cl2/CH4/H2/Ar - 20°C
    • NOTE: Rates in these 2021-09 characterizations are lower than current due to a software timing bug, fixed in 2022-01
  • See Operating Procedure for full traveler and post-cleaning.

GaAs Etch (Oxford ICP Etcher)

This recipe also provides a starting point for GaSb-based etches.

  • GaAs-based materials - etch recipe available on tool - provided by Oxford, not yet qualified internally
  • See Operating Procedure for full traveler and post-cleaning.

GaN Etch (Oxford ICP Etcher)

  • GaN-based materials - etch recipe available on tool - provided by Oxford, not yet qualified internally
  • See Operating Procedure for full traveler and post-cleaning.

GaN Atomic Layer Etching (Oxford ICP Etcher)

GaN-ALE Recipe written and tested by users - contact supervisor for use.

Si Deep RIE (PlasmaTherm/Bosch Etch)

This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!
The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
For Deep Silicon Etching, the Plasma-Therm DSE-iii is often used.  Some single-step Silicon etching is still performed on the SLR Fluorine ICP, due to the slower etch rate.

Bosch and Release Etch (Si Deep RIE)

  • Bosch and Release Processes
    • Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
    • Etch rate depends on area of exposed silicon being etched.
    • Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
    • SiO2 (PECVD) mask has ~100:1 selectivity
    • Thermal SiO2 has ~300:1 selectivity.

Single-step Si Etching (not Bosch Process!) (Si Deep RIE)