Difference between revisions of "ICP Etching Recipes"

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=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=
 
=[[DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)]]=
  
== Edge-Bead Removal ==
+
==Edge-Bead Removal==
 
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!
 
Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!
* [[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
+
 
** If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
+
*[[ASML DUV: Edge Bead Removal via Photolithography|Edge Bead Removal via Photolithography]]: use a custom metal mask to pattern the photoresist with a flood exposure.
 +
**If you are etching fully through a wafer, remember that removal of edge-bead will cause full etching in the exposed areas. To prevent a wafer from falling into the machine after the etch, you can [[Packaging Recipes#Wafer Bonder .28Logitech WBS7.29|mount to a carrier wafer using wax]].
  
 
==High Rate Bosch Etch (DSEIII)==
 
==High Rate Bosch Etch (DSEIII)==
 +
 
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.
 
*[//wiki.nanotech.ucsb.edu/wiki/images/4/4a/10-Si_Etch_Bosch_DSEIII.pdf Bosch Process Recipe and Characterization] - Standard recipe on the tool.
 
**Recipe Name: "'''''Plasma-Therm Standard DSE'''''" (''Production'' - copy to your ''Personal'' category)
 
**Recipe Name: "'''''Plasma-Therm Standard DSE'''''" (''Production'' - copy to your ''Personal'' category)
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.  
+
**Standard [https://en.wikipedia.org/wiki/Deep_reactive-ion_etching#Bosch_process Bosch Process] for high aspect-ratio, high-selectivity Silicon etching.
 
**Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
 
**Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
 
***To reduce roughening/grassing (black silicon), reduce Dep step time by ~20%.
 
***To reduce roughening/grassing (black silicon), reduce Dep step time by ~20%.
 
**Patterns with different etched areas will have different "optimal" parameters.
 
**Patterns with different etched areas will have different "optimal" parameters.
**Approx Selectivity to Photoresist: 60-80 or better.  Larger open area, lower selectivity and lower etch rate.  
+
**Approx Selectivity to Photoresist: 60-80 or better.  Larger open area, lower selectivity and lower etch rate.
  
 
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==
 
==Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)==
 +
 
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
 
*[//wiki.nanotech.ucsb.edu/wiki/images/8/8f/10-Si_Etch_Single_Step_Smooth_Sidewall_DSEIII.pdf Single Step Silicon Etch Recipe and Characterization]
 
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
 
**Recipe Name: "'''''Nano Trench Etch'''''" (''Production'' - copy to your ''Personal'' category)
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
+
**Used instead of Bosch Process, to avoid scalloping on the sidewall.
 
**Lower selectivity, lower etch rate, smoother sidewalls.
 
**Lower selectivity, lower etch rate, smoother sidewalls.
  
 
=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=
 
=[[Fluorine ICP Etcher (PlasmaTherm/SLR Fluorine ICP)|PlasmaTherm/SLR Fluorine Etcher]]=
==Si Etching==
+
==Si Etching (Fluorine ICP Etcher)==
  
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
+
*[//wiki.nanotech.ucsb.edu/wiki/images/b/b8/SLR_-_SiVertHF.pdf SiVertHF] - Si Vertical Etch using C<sub>4</sub>F<sub>8</sub>/SF<sub>6</sub>/CF<sub>4</sub> and resist mask
**Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
+
**Etch Rates: Si ≈ 300-350 nm/min; SiO<sub>2</sub> ≈ 30-35 nm/min
 
**89-90 degree etch angle, ie, vertical.
 
**89-90 degree etch angle, ie, vertical.
 +
**Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO<sub>2</sub> etch (below) to remove native oxide on Si. This can be performed ''in situ'' before the Si etch.
  
==SiO2 Etching==
+
==SiO2 Etching (Fluorine ICP Etcher)==
  
 
*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
 
*[//wiki.nanotech.ucsb.edu/w/images/f/f6/SiO2_Etch%2C_Ru_HardMask_-_Fluorine_ICP_Etch_Process_-_Ning_Cao_2019-06.pdf SiO2 Etching using Ruthenium Hardmask] - Full Process Traveler
 
**''Ning Cao & Bill Mitchell, 2019-06''
 
**''Ning Cao & Bill Mitchell, 2019-06''
 
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
 
**''High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.''
**''Variations in SiO<sub>2</sub> etch Bias Power: 50/200/400W bias.''
+
**''Variations in SiO<sub>2</sub> etch Bias Power: 50 / 200 / 400W bias.''
 
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
 
**Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
**SiO<sub>2</sub> selectivity to Ru: 40 for Bias=200W
+
**200W Bias:
**SiO<sub>2</sub> etch rate: 450nn/min for Bias=200W
+
***SiO<sub>2</sub> selectivity to Ru: 38
 +
***SiO<sub>2</sub> etch rate: 471nm/min
 +
**50W Bias:
 +
***Higher selectivity to photoresist: TBD
 +
***SiO<sub>2</sub> selectivity to Ru: 36
 +
***SiO<sub>2</sub> etch rate: 263nm/min
 +
**This etch is detailed in the following article: [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell ''et al.'', JVST-A, May 2021]]
 +
 
 +
==Photoresist & ARC (Fluorine ICP Etcher)==
 +
Chain multiple Recipes in a Flow, to allow you to to do ''in situ'' BARC etching, and follow up with ''in situ'' Photoresist Strip.
 +
 
 +
*Etching [[Stepper Recipes#DUV-42P|DUV42P-6]] Bottom Anti-Reflection Coating
 +
**~60nm thick (2500krpm)
 +
**O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
 +
**1min
 +
*Photoresist Strip + Polymer Removal
 +
**O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
 +
**Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.
 +
 
 +
==Historical Data (Fluorine ICP Etcher)==
 +
 
 +
===SiO2 Etch Historical Data===
 +
 
 +
*[[Test Data of Etching SiO2 with CHF3/CF4-Fluorine ICP Etcher|Test Data of Etching SiO<sub>2</sub> with CHF3/CF4-Fluorine ICP Etcher]]
 +
 
 +
==Cleaning Procedures (Fluorine ICP Etcher)==
 +
''To Be Added''
  
 
=[[ICP Etch 1 (Panasonic E626I)]]=
 
=[[ICP Etch 1 (Panasonic E626I)]]=
 
==SiO<sub>2</sub> Etching (Panasonic 1)==
 
==SiO<sub>2</sub> Etching (Panasonic 1)==
  
=== Recipes ===
+
===Recipes===
  
 
*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO<sub>2</sub> Vertical Etch Recipe Parameters - CHF<sub>3</sub> "SiOVert"]
 
*[//wiki.nanotech.ucsb.edu/wiki/images/3/3e/Panasonic1-SiO-Etch.pdf SiO<sub>2</sub> Vertical Etch Recipe Parameters - CHF<sub>3</sub> "SiOVert"]
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*[[Test Data of etching SiO2 with CHF3/CF4-ICP1|Test Data of etching SiO2 with CHF3/CF4]]
 
*[[Test Data of etching SiO2 with CHF3/CF4-ICP1|Test Data of etching SiO2 with CHF3/CF4]]
  
=== Recipe Variations ===
+
===Recipe Variations===
 
''Use these to determine how each etch parameter affects the process.''
 
''Use these to determine how each etch parameter affects the process.''
  
* [//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO<sub>2</sub> CHF<sub>3</sub> Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching
+
*[//wiki.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO<sub>2</sub> CHF<sub>3</sub> Etch Variations] - CHF3 with varying Bias and Pressure, Slanted SiO2 etching
  
 
==SiN<sub>x</sub> Etching (Panasonic 1)==
 
==SiN<sub>x</sub> Etching (Panasonic 1)==
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*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl<sub>3</sub>-SF<sub>6</sub>]
 
*[//wiki.nanotech.ucsb.edu/wiki/images/6/60/Panasonic1-GaN-AlGaN-Selective-Etch-Plasma-RIE-ICP-RevA.pdf GaN Selective Etch over AlGaN Recipes BCl<sub>3</sub>-SF<sub>6</sub>]
  
==Photoresist and ARC Etching==
+
==Photoresist and ARC Etching (Panasonic 1)==
[https://wiki.nanotech.ucsb.edu/wiki/index.php/ICP_Etching_Recipes#Photoresist_and_ARC_etching_2 Please see the recipes for Panasonic ICP#2] - the same recipes apply.  
+
[https://wiki.nanotech.ucsb.edu/w/index.php?title=ICP_Etching_Recipes#Photoresist_and_ARC_etching_.28Panasonic_2.29 Please see the recipes for Panasonic ICP#2] - the same recipes apply.  
  
 
Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.
 
Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.
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*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl<sub>2</sub>N<sub>2</sub>]
 
*[//wiki.nanotech.ucsb.edu/wiki/images/f/ff/16-GaAs_etch-ICP-2.pdf GaAs Etch Recipes - Panasonic 2 - Cl<sub>2</sub>N<sub>2</sub>]
  
==Photoresist and ARC etching==
+
==Photoresist and ARC etching (Panasonic 2)==
 
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:
 
Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:
  
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==Ru (Ruthenium) Etch (Panasonic 2)==
 
==Ru (Ruthenium) Etch (Panasonic 2)==
TALK TO BILL BEFORE PUBLISHING WORK USING THIS ETCH.  We are currently writing a paper on this etch.
 
  
 
*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
 
*[https://wiki.nanotech.ucsb.edu/wiki/images/e/e9/194_Ru_Etch_O2%2CCl2.pdf Ru Etch] - ''[[Bill Mitchell]] 2019-09-19''
**''BillM is currently writing a publication on this etch - please discuss with [[Bill Mitchell|Bill]] before submitting any publications using this etch.''
+
**''This etch is used in the following publication:'' [[Template:Publications#Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask|W.J. Mitchell, "Highly Selective and Vertical Etch of Silicon Dioxide using Ruthenium Films as an Etch Mask" (JVST-A, 2021)]]
  
 
=[[ICP-Etch (Unaxis VLR)]]=
 
=[[ICP-Etch (Unaxis VLR)]]=
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==GaSb Etch (Unaxis VLR)==
 
==GaSb Etch (Unaxis VLR)==
  
 +
= [[Oxford ICP Etcher (PlasmaPro 100 Cobra)]] =
 +
 +
== InP Ridge Etch (Oxford ICP Etcher) ==
 +
InP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
 +
 +
=== Low-Temp (60°C) Process ===
 +
 +
* [[Low-Temp InP Ridge Etch Characterization]] - ''To Be Added''
 +
 +
=== High-Temp (200°C) Process ===
 +
 +
* [[High-Temp InP Ridge Etch Characterization]] - ''To Be Added''
 +
 +
== InP Grating Etch (Oxford ICP Etcher) ==
 +
InP/InGaAsP etches were characterized with '''no''' mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).
 +
 +
* [[Low-Temp InP Ridge Etch Characterization|InP/InGaAsP Grating Etch Characterization]] - ''To Be Added''
  
 
=[[Si Deep RIE (PlasmaTherm/Bosch Etch)]]=
 
=[[Si Deep RIE (PlasmaTherm/Bosch Etch)]]=

Revision as of 12:52, 4 September 2021

Back to Dry Etching Recipes.

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

Edge-Bead Removal

Make sure to remove photoresist from edges of wafer, or PR may stick to the top-side wafer clamp and destroy your wafer during unload!

High Rate Bosch Etch (DSEIII)

  • Bosch Process Recipe and Characterization - Standard recipe on the tool.
    • Recipe Name: "Plasma-Therm Standard DSE" (Production - copy to your Personal category)
    • Standard Bosch Process for high aspect-ratio, high-selectivity Silicon etching.
    • Cycles between polymer deposition "Dep" / Polymer etch "Etch A" / Si etch "Etch B" steps. Step Times gives fine control.
      • To reduce roughening/grassing (black silicon), reduce Dep step time by ~20%.
    • Patterns with different etched areas will have different "optimal" parameters.
    • Approx Selectivity to Photoresist: 60-80 or better. Larger open area, lower selectivity and lower etch rate.

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

PlasmaTherm/SLR Fluorine Etcher

Si Etching (Fluorine ICP Etcher)

  • SiVertHF - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
    • Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
    • 89-90 degree etch angle, ie, vertical.
    • Due to high selectivity against SiO2, it may be necessary to run a ~10sec 50W SiO2 etch (below) to remove native oxide on Si. This can be performed in situ before the Si etch.

SiO2 Etching (Fluorine ICP Etcher)

  • SiO2 Etching using Ruthenium Hardmask - Full Process Traveler
    • Ning Cao & Bill Mitchell, 2019-06
    • High-selectivity and deep etching using sputtered Ru hardmask and I-Line litho.
    • Variations in SiO2 etch Bias Power: 50 / 200 / 400W bias.
    • Ru etch selectivity to PR: 0.18 (less than 1): 150nm Ru / 800nm PR
    • 200W Bias:
      • SiO2 selectivity to Ru: 38
      • SiO2 etch rate: 471nm/min
    • 50W Bias:
      • Higher selectivity to photoresist: TBD
      • SiO2 selectivity to Ru: 36
      • SiO2 etch rate: 263nm/min
    • This etch is detailed in the following article: W.J. Mitchell et al., JVST-A, May 2021

Photoresist & ARC (Fluorine ICP Etcher)

Chain multiple Recipes in a Flow, to allow you to to do in situ BARC etching, and follow up with in situ Photoresist Strip.

  • Etching DUV42P-6 Bottom Anti-Reflection Coating
    • ~60nm thick (2500krpm)
    • O2=20sccm / 10mT / RF1(bias)=100W / RF2(icp)=0W
    • 1min
  • Photoresist Strip + Polymer Removal
    • O2=100sccm / 5mT / RF1(bias)=10W / RF2(icp)=825W
    • Use laser monitor to check for complete removal, overetch to remove Fluorocarbon polymers.

Historical Data (Fluorine ICP Etcher)

SiO2 Etch Historical Data

Cleaning Procedures (Fluorine ICP Etcher)

To Be Added

ICP Etch 1 (Panasonic E626I)

SiO2 Etching (Panasonic 1)

Recipes

Historical Data (SiO2, Panasonic 1)

Recipe Variations

Use these to determine how each etch parameter affects the process.

SiNx Etching (Panasonic 1)

Al Etch (Panasonic 1)

Cr Etch (Panasonic 1)

Ta Etch (Panasonic 1)

Ti Etch (Panasonic 1)

W-TiW Etch (Panasonic 1)

GaAs-AlGaAs Etch (Panasonic 1)

GaN Etch (Panasonic 1)

Photoresist and ARC Etching (Panasonic 1)

Please see the recipes for Panasonic ICP#2 - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

SiC Etch (Panasonic 1)

Sapphire Etch (Panasonic 1)

Old Deleted Recipes

Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact Don and he'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

ICP Etch 2 (Panasonic E640)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

SiO2 Etching (Panasonic 2)

Recipes

Historical Data (SiO2 Etch, Panasonic 2)

Recipe Variations

Use these to determine how each etch parameter affects the process.

SiNx Etching (Panasonic 2)

Al Etch (Panasonic 2)

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry (click for plots of etch rate)

Contributed by Brian Markman, 2018

  • BCl3 = 30sccm
  • Pressure = 0.50 Pa
  • ICP Source RF = 500
  • Bias RF = 50W or 250W (250W can burn PR)
  • Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
  • Etch Rate 50W: 0.66nm/sec
  • Etch Rate 250W: 1.0 nm/sec

GaAs Etch (Panasonic 2)

Photoresist and ARC etching (Panasonic 2)

Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

ARC Etching: DUV-42P or AR6

  • O2 = 40 sccm // 0.5 Pa
  • ICP = 75W // RF = 75W
  • 45 sec for full etching of DUV-42P (same as for AR6; 2018-2019, Demis/BrianT)

UV6-0.8 Etching

Works very well for photoresist stripping

  • O2 = 40 sccm // 1.0 Pa
  • ICP = 350W // RF = 100W
  • Etch Rate = 518.5nm / 1min (2019, Demis)
  • 2m30sec to fully remove with ~200% overetch

Ru (Ruthenium) Etch (Panasonic 2)

ICP-Etch (Unaxis VLR)

GaAs-AlGaAs Etch (Unaxis VLR)

InP-InGaAs-InAlAs Etch (Unaxis VLR)

GaN Etch (Unaxis VLR)

GaSb Etch (Unaxis VLR)

Oxford ICP Etcher (PlasmaPro 100 Cobra)

InP Ridge Etch (Oxford ICP Etcher)

InP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).

Low-Temp (60°C) Process

High-Temp (200°C) Process

InP Grating Etch (Oxford ICP Etcher)

InP/InGaAsP etches were characterized with no mounting adhesive used, 1/4-wafer of 50mm wafer placed on Silicon carriers (rough side up).

Si Deep RIE (PlasmaTherm/Bosch Etch)

This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!
The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
For Deep Silicon Etching, the Plasma-Therm DSE-iii is often used.  Some single-step Silicon etching is still performed on the SLR Fluorine ICP, due to the slower etch rate.

Bosch and Release Etch (Si Deep RIE)

  • Bosch and Release Processes
    • Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
    • Etch rate depends on area of exposed silicon being etched.
    • Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
    • SiO2 (PECVD) mask has ~100:1 selectivity
    • Thermal SiO2 has ~300:1 selectivity.

Single-step Si Etching (not Bosch Process!) (Si Deep RIE)