Difference between revisions of "ICP Etching Recipes"

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(→‎SiO2 Etching (Panasonic 1): added historical data section)
(→‎SiO2 Etching (Panasonic 2): added section headings)
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*[//www.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO<sub>2</sub> CHF<sub>3</sub> Etch Variations]
 
*[//www.nanotech.ucsb.edu/wiki/images/5/5e/Panasonic1-SiO2-Data-Process-Variation-CHF3-revA.pdf SiO<sub>2</sub> CHF<sub>3</sub> Etch Variations]
  
=== Historical Data (SiO2, Panasonic 1) ===
+
===Historical Data (SiO2, Panasonic 1)===
  
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Florine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Florine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
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==SiO<sub>2</sub> Etching (Panasonic 2)==
 
==SiO<sub>2</sub> Etching (Panasonic 2)==
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=== Recipes ===
  
 
*[//www.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO<sub>2</sub> Vertical Etch Recipe - CHF<sub>3</sub> "SiOVert"]
 
*[//www.nanotech.ucsb.edu/wiki/images/d/d5/Panasonic2-SiOx-Recipe.pdf SiO<sub>2</sub> Vertical Etch Recipe - CHF<sub>3</sub> "SiOVert"]
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*[//www.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]
 
*[//www.nanotech.ucsb.edu/wiki/images/9/9e/33-Etching_SiO2_with_Vertical_Side-wall.pdf SiO<sub>2</sub> Vertical Etch Recipe#2 - CF<sub>4</sub>/CHF<sub>3</sub>]
 
*[//www.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]
 
*[//www.nanotech.ucsb.edu/wiki/images/1/1e/Panasonic2-ICP-Plasma-Etch-SiO2-nanoscale-rev1.pdf SiO<sub>2</sub> Nanoscale Etch Recipe - CHF<sub>3</sub>/O<sub>2</sub>]
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=== Historical Data (SiO2 Etch, Panasonic 2) ===
 +
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Fluorine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
 
*[[Test Data of etching SiO2 with CHF3/CF4/O2 (using this recipe only for Fluorine etch of the underneath layer)|Test Data of etching SiO2 with CHF3/CF4/O2]]
 
*[[Test Data of etching SiO2 with CHF3/CF4]]
 
*[[Test Data of etching SiO2 with CHF3/CF4]]
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 +
=== Recipe Variations ===
 +
''Use these to determine how each etch parameter affects the process.''
 +
 
*[https://www.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipe]
 
*[https://www.nanotech.ucsb.edu/wiki/images/1/1e/05-SiO2_Nano-structure_Etch.pdf Angled SiO2 sidewall recipe]
  

Revision as of 09:02, 17 January 2020

Back to Dry Etching Recipes.

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

High Rate Bosch Etch (DSEIII)

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

PlasmaTherm/SLR Fluorine Etcher

Si Etching

  • SiVertHF - Si Vertical Etch using C4F8/SF6/CF4 and resist mask
    • Etch Rates: Si ≈ 300-350 nm/min; SiO2 ≈ 30-35 nm/min
    • 89-90 degree etch angle, ie, vertical.

SiO2 Etching

  • Recipes available, to be characterized/added.

ICP Etch 1 (Panasonic E626I)

SiO2 Etching (Panasonic 1)

Historical Data (SiO2, Panasonic 1)

SiNx Etching (Panasonic 1)

Al Etch (Panasonic 1)

Cr Etch (Panasonic 1)

Ta Etch (Panasonic 1)

Ti Etch (Panasonic 1)

W-TiW Etch (Panasonic 1)

GaAs-AlGaAs Etch (Panasonic 1)

GaN Etch (Panasonic 1)

Photoresist and ARC Etching

Please see the recipes for Panasonic ICP#2 - the same recipes apply.

Etching of DUV42P at standard spin/bake parameters also completes in 45 seconds.

SiC Etch (Panasonic 1)

Sapphire Etch (Panasonic 1)

Old Deleted Recipes

Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact Don and he'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

ICP Etch 2 (Panasonic E640)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

SiO2 Etching (Panasonic 2)

Recipes

Historical Data (SiO2 Etch, Panasonic 2)

Recipe Variations

Use these to determine how each etch parameter affects the process.

SiNx Etching (Panasonic 2)

Al Etch (Panasonic 2)

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry (click for plots of etch rate)

Contributed by Brian Markman, 2018

  • BCl3 = 30sccm
  • Pressure = 0.50 Pa
  • ICP Source RF = 500
  • Bias RF = 50W or 250W (250W can burn PR)
  • Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
  • Etch Rate 50W: 0.66nm/sec
  • Etch Rate 250W: 1.0 nm/sec

GaAs Etch (Panasonic 2)

Photoresist and ARC etching

Basic recipes for etching photoresist and Bottom Anti-Reflection Coating (BARC) underlayers are as follows:

ARC Etching: DUV-42P or AR6

  • O2 = 40 sccm // 0.5 Pa
  • ICP = 75W // RF = 75W
  • 45 sec for full etching of DUV-42P (same for AR6)

UV6-0.8 Etching

Works very well for photoresist stripping

  • O2 = 40 sccm // 1.0 Pa
  • ICP = 350W // RF = 100W
  • Etch Rate = 518.5nm / 1min
  • 2m30sec to fully remove with ~200% overetch

Ru (Ruthenium) Etch (Panasonic 2)

TALK TO BILL BEFORE PUBLISHING WORK USING THIS ETCH.  We are currently writing a paper on this etch.
  • Ru Etch - Bill Mitchell 2019-09-19
    • BillM is currently writing a publication on this etch - please discuss with Bill before submitting any publications using this etch.

ICP-Etch (Unaxis VLR)

GaAs-AlGaAs Etch (Unaxis VLR)

InP-InGaAs-InAlAs Etch (Unaxis VLR)

GaN Etch (Unaxis VLR)

GaSb Etch (Unaxis VLR)

Si Deep RIE (PlasmaTherm/Bosch Etch)

This tool does not exist in this configuration any more, so these recipes are for Reference purposes Only!!!
The machine was upgraded to be the new Plasma-Therm Fluorine ICP Etcher - the chamber configuration is now different, making these recipes invalid.
For Deep Silicon Etching, the Plasma-Therm DSE-iii is often used.  Some single-step Silicon etching is still performed on the SLR Fluorine ICP, due to the slower etch rate.

Bosch and Release Etch (Si Deep RIE)

  • Bosch and Release Processes
    • Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
    • Etch rate depends on area of exposed silicon being etched.
    • Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
    • SiO2 (PECVD) mask has ~100:1 selectivity
    • Thermal SiO2 has ~300:1 selectivity.

Single-step Si Etching (not Bosch Process!) (Si Deep RIE)