Difference between revisions of "ICP Etching Recipes"

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==InP-InGaAs-InAlAs Etch (Unaxis VLR)==
 
==InP-InGaAs-InAlAs Etch (Unaxis VLR)==
 
*[[media:18-InP-based etching-Cl2N2Ar.pdf|InP-based Material Etch Profile (Cl<sub>2</sub>N<sub>2</sub>Ar200C)]]
 
*[[media:18-InP-based etching-Cl2N2Ar.pdf|InP-based Material Etch Profile (Cl<sub>2</sub>N<sub>2</sub>Ar200C)]]
*[[media:17-InP&InGaAs etch-Cl2H2Ar-Unaxis-VLR.pdf|InP-InGaAs Etch Profile (Cl<sub>2</sub>H<sub>2</sub> Ar 200C)]]
+
*[[media:17-InP&InGaAs etch-Cl2H2Ar-Unaxis-VLR.pdf|InP-InGaAs Etch Profile (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)]]
 
*[[media:43-Issue with the etch of InP-InGaAs-and- InAlAs-b.pdf|InGaAs-InAlAs Etch Issure (Cl<sub>2</sub>H<sub>2</sub> Ar 200C)]]
 
*[[media:43-Issue with the etch of InP-InGaAs-and- InAlAs-b.pdf|InGaAs-InAlAs Etch Issure (Cl<sub>2</sub>H<sub>2</sub> Ar 200C)]]
*[[media:50-InP Etch-2-17-2016.pdf|InP Etch (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)2-17-2016]]
 
 
*[[InP Etch Test Result in Details|InP Etch Historical Data (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)]]  
 
*[[InP Etch Test Result in Details|InP Etch Historical Data (Cl<sub>2</sub>H<sub>2</sub>Ar 200C)]]  
 
*[[InP Etch Rate and Selectivity (InP/SiO2)|InP Etch Test]]
 
*[[InP Etch Rate and Selectivity (InP/SiO2)|InP Etch Test]]

Revision as of 14:34, 29 June 2018

Back to Dry Etching Recipes.

DSEIII_(PlasmaTherm/Deep_Silicon_Etcher)

High Rate Bosch Etch (DSEIII)

Single-Step Low Etch Rate Smooth Sidewall Process (DSEIII)

Si Deep RIE (PlasmaTherm/Bosch Etch)

Bosch and Release Etch (Si Deep RIE)

  • Bosch and Release Processes
    • Ideal for deep (>>1µm), vertical etching of Silicon. Through-wafer etches are possible (requires carrier wafer).
    • Etch rate depends on area of exposed silicon being etched.
    • Al2O3 mask (ALD or Sputter) has >9000:1 selectivity
    • SiO2 (PECVD) mask has ~100:1 selectivity
    • Thermal SiO2 has ~300:1 selectivity.

Single-step Si Etching (not Bosch Process!) (Si Deep RIE)

ICP Etch 1 (Panasonic E626I)

SiO2 Etching (Panasonic 1)

SiNx Etching (Panasonic 1)

Al Etch (Panasonic 1)

Cr Etch (Panasonic 1)

Ti Etch (Panasonic 1)

W-TiW Etch (Panasonic 1)

GaAs-AlGaAs Etch (Panasonic 1)

GaN Etch (Panasonic 1)

SiC Etch (Panasonic 1)

Sapphire Etch (Panasonic 1)

Old Deleted Recipes

Since there are a limited number of recipe slots on the tool, we occasionally have to delete old, unused recipes.

If you need to free up a recipe slot, please contact Don and he'll help you find an old recipe to replace. We take photographs of old recipes, and save them in case a group needs to revive the recipe. Contact us if your old recipe went missing.

ICP Etch 2 (Panasonic E640)

Recipes starting points for materials without processes listed can be obtained from Panasonic1 recipe files. The chambers are slightly different, but essentially the same, requiring only small program changes to obtain similar results.

SiO2 Etching (Panasonic 2)

SiNx Etching (Panasonic 2)

Al Etch (Panasonic 2)

Al2O3 Etching (Panasonic 2)

ALD Al2O3 Etch Rates in BCl3 Chemistry (click for plots of etch rate)

Contributed by Brian Markman, 2018

  • BCl3 = 30sccm
  • Pressure = 0.50 Pa
  • ICP Source RF = 500
  • Bias RF = 50W or 250W (250W can burn PR)
  • Cooling He Flow/Pressure = 15.0 sccm / 400 Pa
  • Etch Rate 50W: 0.66nm/sec
  • Etch Rate 250W: 1.0 nm/sec

GaAs Etch (Panasonic 2)

Photoresist and ARC etching

Basic recipes for etching photoresist and Anti-Reflection Coating (ARC) underlayers are as follows:

ARC Etching: DUV-42P or AR6

  • O2 = 40 sccm // 0.5 Pa
  • ICP = 75W // RF = 75W
  • 45 sec for full etching of DUV-42P (same for AR6)

UV6-0.8 Etching

Works very well for photoresist stripping

  • O2 = 40 sccm // 1.0 Pa
  • ICP = 350W // RF = 100W
  • Etch Rate = 518.5nm / 1min
  • 2m30sec to fully remove with ~50% overetch

ICP-Etch (Unaxis VLR)

GaAs-AlGaAs Etch (Unaxis VLR)

InP-InGaAs-InAlAs Etch (Unaxis VLR)

GaN Etch (Unaxis VLR)

GaSb Etch (Unaxis VLR)